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delic-lc delic-pb dsp embedded line and port interface controller peb 20570 version 3.1 peb 20571 version 3.1 data sheet, ds 1, march 2001 wired communications never stop thinking.
edition 2001-03-19 published by infineon technologies ag, st.-martin-strasse 53, d-81541 mnchen, germany ? infineon technologies ag 3/19/01. all rights reserved. attention please! the information herein is given to describe certain components and shall not be considered as warranted characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. infineon technologies is an approved cecc manufacturer. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologies office in germany or our infineon technologies representatives worldwide (see address list). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
wired communications p r e l i m i n a r y delic-lc delic-pb dsp embedded line and port interface controller peb 20570 version 3.1 peb 20571 version 3.1 data sheet, ds 1, march 2001 never stop thinking.
for questions on technology, delivery and prices please contact the infineon technologies offices in germany or the infineon technologies companies and representatives worldwide: see our webpage at http://www.infineon.com peb 20570 preliminary revision history: 2001-03-19 ds 1 previous version: page subjects (major changes since last revision)
peb 20570 peb 20571 table of contents page data sheet 2001-03-19 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.1 delic-lc key features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2 delic-pb key features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.3 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.4 typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.4.1 applications for delic-lc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.4.2 applications for delic-pb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 pin diagram delic-lc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 pin diagram delic-pb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.3 pin definitions and functions for delic-lc . . . . . . . . . . . . . . . . . . . . . . . 12 2.4 pin definitions and functions for delic-pb . . . . . . . . . . . . . . . . . . . . . . . 24 2.5 strap pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3 interface description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.1 overview of interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.2 iom-2000 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.2.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.2.2 iom-2000 frame structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.2.2.1 data interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.2.2.2 command and status interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.2.3 upn state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.2.3.1 info structure on the upn interface . . . . . . . . . . . . . . . . . . . . . . . . 48 3.2.3.2 upn mode state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.2.4 s/t state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 3.2.4.1 lt-s mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 3.2.4.2 lt-t mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 3.3 iom?-2 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 3.3.1 signals / channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 3.4 p interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 3.4.1 intel/infineon or motorola mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 3.4.2 de-multiplexed or multiplexed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 3.4.3 dma or non-dma mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 3.4.4 delic external interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 3.5 jtag test interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 3.5.1 boundary scan test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 3.5.2 tap controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 4.1 functional overview and block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.2 iom-2000 transceiver unit (transiu) . . . . . . . . . . . . . . . . . . . . . . . . . . 71 4.2.1 iom-2000 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 4.2.2 iom-2000 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
peb 20570 peb 20571 table of contents page data sheet 2001-03-19 4.2.3 initialization of the vip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 4.2.4 iom-2000 command and status interface . . . . . . . . . . . . . . . . . . . . . . 72 4.2.4.1 initialization mode command bits . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 4.2.4.2 operational mode command/status bits . . . . . . . . . . . . . . . . . . . . . 72 4.2.4.3 command/status transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 4.2.4.4 command and status format in the data ram . . . . . . . . . . . . . . . . . 74 4.2.5 upn mode frame structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 4.2.6 upn interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 4.2.7 upn framing bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 4.2.7.1 framing bit (lf-bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 4.2.7.2 multiframing bit (m-bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 4.2.7.3 dc-balancing bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 4.2.7.4 upn mode data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 4.2.7.5 upn scrambler/descrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 4.2.8 dect synchronization for upn- interface . . . . . . . . . . . . . . . . . . . . . . 82 4.2.9 s/t interface frame structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 4.2.9.1 lt-s mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 4.2.9.2 lt-t mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 4.2.10 s/t mode control and framing bits on iom-2000 . . . . . . . . . . . . . . . . 90 4.2.10.1 framing bit (f-bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 4.2.10.2 multiframing bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 4.2.10.3 fa/n bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 4.2.10.4 dc-balancing bit (l-bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 4.2.11 iom-2000 data interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 4.2.11.1 s/t mode data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 4.2.12 test loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 4.3 iom-2 unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 4.3.1 iomu features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 4.3.2 iomu functional and operational description . . . . . . . . . . . . . . . . . . . 96 4.3.2.1 frame-wise buffer swapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 4.3.2.2 dsp inaccessible buffer (i-buffer) logical structure . . . . . . . . . . . . . 96 4.3.2.3 dsp access to the d-buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 4.3.2.4 circular buffer architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 4.3.2.5 iom-2 interface data rate modes . . . . . . . . . . . . . . . . . . . . . . . . . . 100 4.3.2.6 iomu serial data processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 4.3.2.7 iomu parallel data processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 4.3.2.8 iom-2 push-pull and open-drain modes . . . . . . . . . . . . . . . . . . . . 102 4.3.2.9 support of drdy signal from quat-s . . . . . . . . . . . . . . . . . . . . . . 103 4.4 pcm unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 4.4.1 pcmu functional and operational description . . . . . . . . . . . . . . . . . . 105 4.4.1.1 frame-wise buffer swapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 4.4.1.2 dsp inaccessible buffer (i-buffer) . . . . . . . . . . . . . . . . . . . . . . . . . . 105
peb 20570 peb 20571 table of contents page data sheet 2001-03-19 4.4.1.3 dsp accessible buffer (d-buffer) . . . . . . . . . . . . . . . . . . . . . . . . . . 106 4.4.1.4 pcmu interface data rate modes . . . . . . . . . . . . . . . . . . . . . . . . . 107 4.4.1.5 pcmu serial data processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 4.4.1.6 pcmu parallel data processing . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 4.4.1.7 pcmu tri-state control logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 4.5 a-/-law conversion unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 4.6 hdlc unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 4.6.1 hdlc overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 4.6.2 hdlcu operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 4.6.2.1 initialization of the hdlcu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 4.6.2.2 transmitting a message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 4.6.2.3 ending a transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 4.6.2.4 aborting a transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 4.6.2.5 dsp access to the hdlcu buffers . . . . . . . . . . . . . . . . . . . . . . . . . 116 4.6.3 functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 4.7 ghdlc unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 4.7.1 ghdlc overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 4.7.2 ghdlc general modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . 119 4.7.3 external configuration and handshaking in bus mode . . . . . . . . . . . . 120 4.7.3.1 external tri-state in point-to-multi-point mode . . . . . . . . . . . . . . . . 120 4.7.3.2 arbitration between several ghdlcs . . . . . . . . . . . . . . . . . . . . . . . 120 4.7.4 ghdlc memory allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 4.7.5 ghdlc interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 4.7.6 operational description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 4.7.6.1 ghdlc initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 4.7.7 ghdlc protocol features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 4.7.8 ghdlc possible data rates for the delic-lc/pb . . . . . . . . . . . . . . . 125 4.7.9 ghdlc using external dma controller . . . . . . . . . . . . . . . . . . . . . . . . 126 4.8 dsp control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 4.8.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 4.8.2 dsp address decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 4.8.3 interrupt handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 4.8.4 dsp run time statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 4.8.5 data bus and program bus arbitration . . . . . . . . . . . . . . . . . . . . . . . . 129 4.8.6 boot support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 4.8.7 reset execution and boot strap pin setting . . . . . . . . . . . . . . . . . . . . 130 4.9 general mailbox . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 4.9.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 4.9.2 p mailbox . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 4.9.3 oak mailbox . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 4.10 dma mailbox (delic-pb only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 4.10.1 dma handshake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
peb 20570 peb 20571 table of contents page data sheet 2001-03-19 4.10.1.1 two-cycle dma transfer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 4.10.1.2 fly-by mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 4.10.2 pec mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 4.10.3 transmit = dma = mailbox . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 4.10.4 receive dma mailbox . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 4.10.5 fifo access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 4.11 clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 4.11.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 4.11.2 dsp clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 4.11.3 pcm master/slave mode clocks selection . . . . . . . . . . . . . . . . . . . . . 144 4.11.4 delic clock system synchronization . . . . . . . . . . . . . . . . . . . . . . . . . 144 4.11.5 iom-2 clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 4.11.6 iom-2000 clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 4.11.7 refclk configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 4.11.8 ghdlc clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 5 delic memory structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 5.1 dsp address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 5.1.1 dsp register address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 5.1.2 dsp program address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 5.1.3 dsp data address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 5.2 p address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 6 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 6.1 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 6.2 detailed register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 6.2.1 transiu register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 6.2.1.1 transiu iom-2000 configuration register . . . . . . . . . . . . . . . . . . 161 6.2.1.2 transiu channel configuration registers . . . . . . . . . . . . . . . . . . 162 6.2.1.3 vip command registers (vipcmr0, vipcmr1, vipcmr2) . . . . . 164 6.2.1.4 vip status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 6.2.1.5 transiu initialization channel command register . . . . . . . . . . . . 168 6.2.1.6 transiu initialization channel status register (ticstr) . . . . . . . 173 6.2.1.7 up test loop register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 6.2.1.8 scrambler mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 6.2.1.9 scrambler status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 6.2.2 iomu register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 6.2.2.1 iomu control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 6.2.2.2 iomu status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 6.2.2.3 iomu tri-state control register . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 6.2.2.4 iomu drdy register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 6.2.2.5 iomu data prefix register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 6.2.3 pcmu register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
peb 20570 peb 20571 table of contents page data sheet 2001-03-19 6.2.3.1 pcmu command register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 6.2.3.2 pcmu status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 6.2.3.3 pcmu tri-state control registers . . . . . . . . . . . . . . . . . . . . . . . . . . 185 6.2.3.4 pcmu data prefix register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 6.2.4 a-/-law unit register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 6.2.4.1 a/-law unit control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 6.2.4.2 a/-law input register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 6.2.4.3 a/-law output register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 6.2.5 hdlcu registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 6.2.5.1 hdlcu control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 6.2.5.2 hdlcu status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 6.2.5.3 channel command vector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 6.2.5.4 channel status vector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 6.2.6 ghdlc register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 6.2.6.1 ghdlc test/ normal mode register . . . . . . . . . . . . . . . . . . . . . . . 197 6.2.6.2 ghdlc channel mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 6.2.6.3 ghdlc interrupt register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 6.2.6.4 ghdlc fsc interrupt control register . . . . . . . . . . . . . . . . . . . . . . 200 6.2.6.5 ghdlc receive channel status registers 0..3 . . . . . . . . . . . . . . . 201 6.2.6.6 ghdlc receive data and status . . . . . . . . . . . . . . . . . . . . . . . . . . 203 6.2.6.7 ghdlc mode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 6.2.6.8 ghdlc channel transmit command registers . . . . . . . . . . . . . . . 206 6.2.6.9 async control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 6.2.6.10 lclk0 control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 6.2.6.11 lclk1 control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 6.2.6.12 lclk2 control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 6.2.6.13 lclk3 control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 6.2.6.14 muxes control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 6.2.6.15 ghdlcu frame frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 6.2.7 dcu register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 6.2.7.1 interrupt mask register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 6.2.7.2 status event register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 6.2.7.3 statistics counter register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 6.2.7.4 statistics register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 6.2.8 p configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 6.2.8.1 p interface configuration register . . . . . . . . . . . . . . . . . . . . . . . . . 218 6.2.8.2 interrupt vector register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 6.2.9 p mailbox registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 6.2.9.1 p command register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 6.2.9.2 p mailbox busy register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 6.2.9.3 p mailbox generic data register . . . . . . . . . . . . . . . . . . . . . . . . . 223 6.2.9.4 p mailbox (general and dma mailbox) data registers . . . . . . . . . 224
peb 20570 peb 20571 table of contents page data sheet 2001-03-19 6.2.9.5 dsp command register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 6.2.9.6 dsp mailbox busy register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 6.2.9.7 dsp mailbox generic data register . . . . . . . . . . . . . . . . . . . . . . . . 227 6.2.9.8 dsp mailbox (general and dma mailbox) data registers . . . . . . . 228 6.2.10 dma mailbox registers description . . . . . . . . . . . . . . . . . . . . . . . . . . 229 6.2.10.1 dma mailbox transmit counter register . . . . . . . . . . . . . . . . . . . . 229 6.2.10.2 dma mailbox receive counter register . . . . . . . . . . . . . . . . . . . . . 230 6.2.10.3 dma mailbox interrupt status register . . . . . . . . . . . . . . . . . . . . . . 231 6.2.11 clock generator register description . . . . . . . . . . . . . . . . . . . . . . . . . 232 6.2.11.1 pdc control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 6.2.11.2 pfs control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 6.2.11.3 clkout control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 6.2.11.4 dcxo reference clock select register . . . . . . . . . . . . . . . . . . . . . 235 6.2.11.5 refclk control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 6.2.11.6 dcl_2000 control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 6.2.11.7 dcl control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 6.2.11.8 fsc control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 6.2.11.9 l1_clk control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 6.2.11.10 pfs sync register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 6.2.11.11 real-time counter register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 6.2.11.12 strap status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 7 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 8 electrical characteristics and timing diagrams . . . . . . . . . . . . . . . . 245 8.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 8.2 operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 8.3 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 8.4 capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 8.5 recommended 16.384 mhz crystal parameters . . . . . . . . . . . . . . . . . . 248 8.6 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 8.6.1 dma access timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 8.6.1.1 dma access timing in motorola mode . . . . . . . . . . . . . . . . . . . . . . 249 8.6.1.2 dma access timing in intel/infineon mode . . . . . . . . . . . . . . . . . . . 252 8.6.2 mp access timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 8.6.2.1 mp access timing in motorola mode . . . . . . . . . . . . . . . . . . . . . . . 255 8.6.2.2 mp access timing in intel/infineon mode . . . . . . . . . . . . . . . . . . . . 257 8.6.3 interrupt acknowledge cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . . 260 8.6.4 iom-2 interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 8.6.5 pcm interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 8.6.6 iom-2000 interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 8.6.7 lnc0..3 (local network controller) interface timing . . . . . . . . . . . . . 273 8.6.8 jtag and emulation interface timing . . . . . . . . . . . . . . . . . . . . . . . . . 277
peb 20570 peb 20571 table of contents page data sheet 2001-03-19 9 application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 9.1 delic connection to external microprocessors . . . . . . . . . . . . . . . . . . . 282 9.2 delic worksheets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 9.3 pcm output driver anomaly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 9.4 reset behaviour . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 10 glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 11 index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
peb 20570 peb 20571 list of figures page data sheet 2001-03-19 figure 1 block diagram of the delic-lc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 figure 2 block diagram of the delic-pb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 figure 3 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 4 delic-lc in s/t and upn line cards (up to 8 s/t and 16 upn). . . . . 7 figure 5 delic-lc/pb in uk0 line card for 16 subscribers . . . . . . . . . . . . . . . . 8 figure 6 delic-pb in analog line card for 16 subscribers . . . . . . . . . . . . . . . . 8 figure 7 delic-pb in small pbx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 8 delic-pb in 4 port sdsl line card . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 9 pin configuration delic-lc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 10 pin configuration delic-pb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 11 overview of iom-2000 interface structure (example with one vip) . . 41 figure 12 iom-2000 data sequence (1 vip with 8 channels) . . . . . . . . . . . . . . 43 figure 13 iom-2000 data order (3 vips with 24 channels) . . . . . . . . . . . . . . . . 44 figure 14 iom-2000 cmd/stat handling (1 vip with 8 channels) . . . . . . . . . . 45 figure 15 iom-2000 command/status sequence (3 vips with 24 channels) . . 45 figure 16 upn state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 17 state diagram of lt-s mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 18 lt-t mode state diagram (conditional and unconditional states) . . . 60 figure 19 iom ? -2 interface in digital line card mode . . . . . . . . . . . . . . . . . . . . 63 figure 20 delic in multiplexed and in de-multiplexed bus mode . . . . . . . . . . . 65 figure 21 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 22 u pn interface frame structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 figure 23 ami coding on the up interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 figure 24 handling of upn frame (one channel) . . . . . . . . . . . . . . . . . . . . . . . . 79 figure 25 s/t interface line code (without code violation) . . . . . . . . . . . . . . . . . 83 figure 26 frame structure at reference points s and t (itu i.430). . . . . . . . . . 84 figure 27 reference clock selection for cascaded vips on iom-2000 . . . . . . . 85 figure 28 handling of so frame in lt-s mode (one channel) . . . . . . . . . . . . . . 86 figure 29 d-echo bit generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 figure 30 handling of so frame in lt-t mode (one channel) . . . . . . . . . . . . . . 88 figure 31 collision detection in the lt-t mode . . . . . . . . . . . . . . . . . . . . . . . . . . 90 figure 32 s/q channel assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 figure 33 iomu integration in delic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 figure 34 iomu frame-wise circular-buffer architecture. . . . . . . . . . . . . . . . . . 98 figure 35 the circular-buffer during two consecutive frames. . . . . . . . . . . . . . 99 figure 36 iom-2 interface timing in single/double clock mode . . . . . . . . . . . . 101 figure 37 iom-2 interface open-drain mode . . . . . . . . . . . . . . . . . . . . . . . . . . 102 figure 38 iom-2 interface push-pull mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 figure 39 drdy signal behavior. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 figure 40 drdy sampling timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 figure 41 pcmu integration in delic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 figure 42 iom-2 interface timing in single/double clock mode . . . . . . . . . . . . 108
peb 20570 peb 20571 list of figures page data sheet 2001-03-19 figure 43 a/-law unit integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 figure 44 hdlcu general block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 figure 45 hdlc data flow in receive direction . . . . . . . . . . . . . . . . . . . . . . . . 117 figure 46 data processing in the ghdlc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 figure 47 ghdlc interface lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 figure 48 point-to-multi point bus structure . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 figure 49 ghdlc receive and transmit buffer structure . . . . . . . . . . . . . . . . 124 figure 50 interframe time fill with shared zero . . . . . . . . . . . . . . . . . . . . . . . . 125 figure 51 statistics registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 figure 52 two-cycle dma transfer mode for receive direction . . . . . . . . . . . . 134 figure 53 single cycle dma transfer mode for receive data . . . . . . . . . . . . . . 135 figure 54 single cycle dma transfer mode for transmit data . . . . . . . . . . . . . . 136 figure 55 timing in two-cycle dma mode for transmit direction and infineon/ intel bus type 138 figure 56 timing in two-cycle dma mode for receive direction and infineon/ intel bus type 140 figure 57 delic clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 figure 58 transiu buffer addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 figure 59 dma write-transaction timing in motorola mode . . . . . . . . . . . . . . . 251 figure 60 dma read-transaction timing in motorola mode . . . . . . . . . . . . . . . 252 figure 61 dma write-transaction timing in intel/infineon mode. . . . . . . . . . . . 254 figure 62 dma read-transaction timing in intel/infineon mode . . . . . . . . . . . 254 figure 63 write cycle motorola mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 figure 64 read cycle motorola mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 figure 65 write cycle intel/infineon demultiplexed mode . . . . . . . . . . . . . . . . . 258 figure 66 read cycle intel/infineon demultiplexed mode . . . . . . . . . . . . . . . . . 258 figure 67 write cycle intel/infineon multiplexed mode . . . . . . . . . . . . . . . . . . . 259 figure 68 read cycle in intel/infineon multiplexed mode . . . . . . . . . . . . . . . . . 260 figure 69 interrupt acknowledge cycle timing in motorola mode. . . . . . . . . . . 261 figure 70 interrupt acknowledge cycle timing in intel/infineon mode . . . . . . . 261 figure 71 ireq deactivation timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 figure 72 iom-2 interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 figure 73 drdy timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 figure 74 dcl timing iom-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 figure 75 fsc timing iom-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 figure 76 pfs timing in slave mode (input pcm clocks) . . . . . . . . . . . . . . . . 267 figure 77 pfs timing in master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 figure 78 pfs interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 figure 79 pdc parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 figure 80 pdc timing in input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 figure 81 iom-2000 interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 figure 82 fsc timing iom-2000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
peb 20570 peb 20571 data sheet 14 2001-03-19 preliminary figure 83 lnc0..3 (local network controller) interface timing . . . . . . . . . . . . 274 figure 84 lclk0..3 timing in output mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 figure 85 lclk0..3 timing in input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 figure 86 test-interface (boundary scan) timing . . . . . . . . . . . . . . . . . . . . . . . 278 figure 87 reset indication timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 figure 88 clockout timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 figure 89 l1_clk timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 figure 90 xclk timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 figure 91 refclk timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 figure 92 delic connection to intel 80386ex (demuxed configuration) . . . . 282 figure 93 delic connection to infineon c165 (demuxed configuration). . . . . 283 figure 94 delic-lc pcm unit mode 0 (4 ports with 2 mbit/s) . . . . . . . . . . . . . 284 figure 95 command/ indication handshake of general mailbox. . . . . . . . . . . . 285 figure 96 behavior of output driver if last bit is ? 1 ? . . . . . . . . . . . . . . . . . . . . . 286 figure 97 behavior of output driver if last bit is ? 0 ? . . . . . . . . . . . . . . . . . . . . . 286 figure 98 guaranteed reset behaviour . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
peb 20570 peb 20571 list of tables page data sheet 2001-03-19 table 1 iom ? -2 interface pins (delic-lc) . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 2 iom-2000 interface / lnc port 1 (delic-lc) . . . . . . . . . . . . . . . . . . . 14 table 3 lnc port 0 (delic-lc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 4 microprocessor bus interface pins (delic-lc). . . . . . . . . . . . . . . . . . 16 table 5 pcm interface ports 0 ... 3 / lnc ports 2 ... 3 (delic-lc) . . . . . . . . . 18 table 6 clock generator pins (delic-lc) (additionally to iom/pcm clocks) . 20 table 7 power supply pins (delic-lc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 8 jtag and emulation interface pins (delic-lc) . . . . . . . . . . . . . . . . . 22 table 9 test interface pins (delic-lc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 10 iom ? -2 interface pins (delic-pb) . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 11 iom-2000 interface / lnc port 1 (delic-pb) . . . . . . . . . . . . . . . . . . . 26 table 12 lnc port 0 (delic-pb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 13 microprocessor bus interface pins (delic-pb) . . . . . . . . . . . . . . . . . 28 table 14 pcm interface ports 0 ... 3 / lnc ports 2 ... 3 (delic-pb) . . . . . . . . . 31 table 15 clock generator pins (delic-pb) (additionally to iom/pcm clocks). 34 table 16 power supply pins (delic-pb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 17 jtag and emulation interface pins (delic-pb) . . . . . . . . . . . . . . . . . 36 table 18 test interface pins (delic-pb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 19 strap pins (evaluated during reset) . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 20 control bits in s/t mode on dr line . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 21 control bits in s/t mode on dx line . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 22 info structure on upn interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 23 upn state machine codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 24 lt-s state machine codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 25 lt-t mode state machine codes (conditional states) . . . . . . . . . . . . 58 table 26 tap controller instruction codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 27 differences between delic-lc and delic-pb . . . . . . . . . . . . . . . . . 69 table 28 d-echo bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 29 s/t mode multiframe bit positions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 30 i-buffer logical memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 table 31 d-buffer address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 table 32 dcl frequency in different iom-2 modes. . . . . . . . . . . . . . . . . . . . . 100 table 33 i-buffer logical memory mapping of input buffers. . . . . . . . . . . . . . . 106 table 34 i-buffer logical memory mapping of output buffers . . . . . . . . . . . . . 106 table 35 dsp access to d-buffer input blocks . . . . . . . . . . . . . . . . . . . . . . . . 106 table 36 dsp access to d-buffer output blocks . . . . . . . . . . . . . . . . . . . . . . . 107 table 37 pcm tsc in 4 x 32 ts mode (4 x 2 mbit/s) . . . . . . . . . . . . . . . . . . . 109 table 38 pcm tsc in 2 x 64 ts mode (2 x 4mbit/s) . . . . . . . . . . . . . . . . . . . . 109 table 39 pcm tsc in 1 x 128 ts (1 x 8 mbit/s) and 1 x 256 ts (1 x 16 mbit/s) (1st half) mode 110 table 40 pcm tsc in 1 x 256 ts (1 x 16 mbit/s) (2nd half) mode . . . . . . . . . 110 table 41 ghdlcu receive buffer configuration . . . . . . . . . . . . . . . . . . . . . . . 123
peb 20570 peb 20571 list of tables page data sheet 2001-03-19 table 42 interrupt map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 table 43 overview of clock signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 table 44 dsp registers address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 table 45 dsp program address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 table 46 occupied dsp data address space . . . . . . . . . . . . . . . . . . . . . . . . . 147 table 47 oak memory mapped registers address space . . . . . . . . . . . . . . . 148 table 48 p address space table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 table 49 transiu register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 table 50 scrambler register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 table 51 iomu register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 table 52 pcmu register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 table 53 a-/-law unit register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 table 54 hdlcu register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 table 55 ghdlc register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 table 56 dcu register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 table 57 p configuration register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 table 58 general mailbox register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 table 59 dma mailbox register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 table 60 clock generator register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 table 61 available isdn modes for each vip channel . . . . . . . . . . . . . . . . . . 162 table 62 tristate control assignment for iom-2 time slots. . . . . . . . . . . . . . . 180 table 63 r/w behavior during dma transactions in normal and in fly-by mode . 249 table 64 dma transaction timing in motorola mode . . . . . . . . . . . . . . . . . . . . 250 table 65 r/w behavior during dma transactions in normal and in fly-by modes. 253 table 66 dma transaction timing in intel/infineon mode . . . . . . . . . . . . . . . . 253 table 67 timing for write cycle in motorola mode . . . . . . . . . . . . . . . . . . . . . . 255 table 68 timing for read cycle in motorola mode . . . . . . . . . . . . . . . . . . . . . 256 table 69 timing for write cycle in intel/infineon demultiplexed mode. . . . . . . 257 table 70 timing for read cycle in intel/infineon demultiplexed mode . . . . . . 258 table 71 timing for write cycle in intel/infineon multiplexed mode . . . . . . . . . 259 table 72 timing for read cycle in intel/infineon multiplexed mode . . . . . . . . 260 table 73 interrupt acknowledge cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . 261 table 74 iom-2 interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 table 75 dcl (iom-2 data clock) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 table 76 fsc (iom-2 and iom-2000 frame-sync) timing . . . . . . . . . . . . . . . 264 table 77 pcm interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 table 78 pdc (pcm data clock) timing in master mode (output mode) . . . . 268 table 79 pdc timing in input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 table 80 iom-2000 interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 table 81 dcl_2000 (iom-2000 data clock) timing . . . . . . . . . . . . . . . . . . . . 272
peb 20570 peb 20571 list of tables page data sheet 2001-03-19 table 82 lnc0..3 interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 table 83 lclk0..3 timing in output mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 table 84 lclk0..3 timing in input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 table 85 clk_dsp input clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 table 86 test interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 table 87 reset and resind (reset indication) timing . . . . . . . . . . . . . . . . . . 278 table 88 clockout timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 table 89 l1_clk timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 table 90 xclk timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 table 91 refclk timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
peb 20570 peb 20571 data sheet 1 2001-03-19 preliminary preface this document provides reference information on the delic-lc/-pb version 3.1. organization of this document this data sheet is divided into 11 chapters and appendices. it is organized as follows: chapter 1 introduction gives a general description of the product and its family, lists the key features, and presents some typical applications. chapter 2 pin description lists pin locations with associated signals, categorizes signals according to function, and describes signals. chapter 3 interface description describes the delic external interfaces. chapter 4 functional description describes the features of the main functional blocks. chapter 5 delic memory structure containes the memory organisation of the oak. chapter 6 register description containes the detailed register description. chapter 7 package outlines chapter 8 electrical characteristics and timing diagrams containes the dc specification. contains the ac specification. chapter 9 application hints provides e.g. a worksheet chapter 10 glossary chapter 11 index your comments we welcome your comments on this document as we are continuously aiming at improving our documentation. please send your remarks and suggestions by e-mail to sc.docu_comments@infineon.com please provide in the subject of your e-mail: device name (delic-lc/ -pb), device number (peb 20570/peb 20571), device version (version 3.1), or and in the body of your e-mail: document type (data sheet), issue date (2001-03-19) and document revision number (ds 1).
peb 20570 peb 20571 introduction data sheet 2 2001-03-19 preliminary 1 introduction the delic and vip chipset realizes multiple isdn s/t and u pn interfaces together with controller functionality typically needed in pbx or central office systems. this functionality comprises voice channel handling, signaling control, layer-1 control, and even signal processing tasks. moreover it provides a programmable master/slave clock generator with 2 plls, an universal p interface and a dma interface. the controller part, delic, is available in two different versions: delic-lc ( peb 20570 ) is a line card controller providing voice channel switching, multiple hdlc and layer-1 control for up to three vips (24 isdn channels). other transceiver ics (32 analog or 16 digital channels) may additionally be connected via iom-2/gci interface. delic-pb (peb 20571 ) additionally provides a programmable telecom dsp including program and data ram. this dsp can be used for layer-1 control, protocol support and signal processing. the flexibility gained by the programmability allows infineon to offer different application specific solutions with the same silicon just by software configuration. a configuration tool assists the user in finding a valid system configuration. even more customer specific dsp-routines can be integrated with the assistance of infineon. the transceiver part, vip , is available in two different versions: vip peb 20590 is the first (8 channel) isdn transceiver that implements multiple u pn and s/t interfaces within one device. the user can decide by programming in which mode a desired channel shall work. a total of 8 channels are provided for layer-1 subscriber or trunk line characteristic. the vip is programmed by the delic via the iom-2000 interface. vip ? s eight channels are programmable in the following maximum partitioning between u pn and s/t channels: vip-8 peb 20591 additionally to the features of the vip, the vip - 8 allows any combination of u pn s/t interface (i.e. each of the 8 channels may be programmed to s/t or u pn mode) max. number of u pn and s/t channels u pn 87654 s/t01234
peb 20570 peb 20571 introduction data sheet 3 2001-03-19 preliminary block diagrams: figure 1 block diagram of the delic-lc figure 2 block diagram of the delic-pb iom-2 / pcm interface iom-2000 interface clocks pcm interface signaling controller jtag switch 256 x 256 ts 24 hdlc controllers p mailbox delic-lc serial port/ i/o-ports pcm iom-2 / pcm iom - 2000 p interface delic-lc-pb1.vsd iom-2 / pcm interface iom-2000 interface clocks pcm interface async/sync controller jtag switch 32 hdlc controllers p mailbox dma mailbox delic-pb serial port/ i/o-ports pcm iom-2 / pcm iom - 2000 p interface program ram data ram dsp voice handling dsp emulation interface delic-lc-pb.vsd
data sheet 4 2001-03-19 type package peb 20571/ peb 20570 p-tqfp-100-3 dsp embedded line and port interface controller delic-lc delic-pb peb 20570 peb 20571 version 3.1 cmos preliminary p-tqfp-100-3 1.1 delic-lc key features delic-lc is optimized for line card applications: one iom-2000 interface supporting three vips i.e. up to 24 isdn channels two iom-2 (gci) ports (configurable as pcm ports) supporting up to 16 isdn channels or 32 analog subscribers four pcm ports with up to 4 x 2.048 mbit/s (4 x 32 ts) or 2 x 4.096 mbit/s or 1 x 8.192 mbit/s switching matrix 256 x 256 ts (8-bit switching) 24 hdlc controllers assignable to any d- or b-channel (at 16 kbit/s or 64 kbit/s) serial communication controller: high-speed signaling channel for 2.048 mbit/s general purpose i/o ports standard multiplexed and de-multiplexed p interface: infineon, intel, motorola programmable pll based master/slave clock generator, providing all system clocks from a single 16.384 mhz crystal source jtag compliant test interface single 3.3 v power supply, 5 v tolerant inputs 1.2 delic-pb key features compared to the delic-lc, having a fixed functionality, the delic-pb provides a high degree of flexibility (in terms of selected number of ports or channels). additionally it features computing power for typical dsp-oriented pbx tasks like conferencing, dtmf etc. a microsoft windows based configuration tool, the configurator, enables to generate an application specific functionality. its features are mainly determined by the firmware of the integrated telecom dsp.
peb 20570 peb 20571 introduction data sheet 5 2001-03-19 preliminary list of maximum available features: one iom-2000 interface supporting up to three vips i.e. up to 24 isdn channels support of dasl mode up to two iom-2 (gci) ports (also configurable as pcm ports) supporting up to 16 isdn channels or 32 analog subscribers up to four pcm ports with up to 4 x 2.048 mbit/s (4 x 32 ts) or 2 x 4.096 mbit/s or 1x8.192mbit/s switching matrix 256 x 256 ts (switching of 4-/8- bit time slots) up to 32 hdlc controllers assignable to any d- or b-channel (at 16 kbit/s or 64 kbit/s) up to 4 serial communication controllers: one of them with up to 8.192 mbit/s data rate general purpose i/o ports dect synchronization support standard multiplexed and de-multiplexed p interface: infineon, intel, motorola dedicated dma support mailbox for 2 dma-channels integrated dsp core oak+ (60 mips for layer 1 control, signalling and dsp- algorithms) 4 kword on-chip program memory 2 kword on-chip data memory 2 kword rom dsp work load measurement for run-time statistics, dsp alive indication on chip debugging unit serial dsp program debugging interface connected via jtag port a-/-law conversion unit programmable pll based master/slave clock generator, providing all system clocks from a single 16.384 mhz crystal source jtag compliant test interface single 3.3 v power supply, 5 v compatible inputs note: as each feature consumes system resources (dsp-mips, memory, port pins), the maximum available number of supported interfaces or hdlc channels is limited by the totally available resources. a system configurator tool ( see delic software user?s manual) helps to determine a valid configuration.
peb 20570 peb 20571 introduction data sheet 6 2001-03-19 preliminary 1.3 logic symbol figure 3 logic symbol lnc or signaling interface delic-lc peb20570 delic-pb peb 20571 clock signals 7 9 14 5 5 27 26 delic-logic-ds.vsd iom-2000/ lnc interface 5 test interface 2 p-tqfp-100-3 iom-2 interfaces pcm/ lnc interfaces p interface power supply jtag interface p-tqfp-100-3
peb 20570 peb 20571 introduction data sheet 7 2001-03-19 preliminary 1.4 typical applications 1.4.1 applications for delic-lc the following two figures show example configurations of delic-lc line card applications for different isdn interface standards. in figure 4 , three vip transceiver ics are connected to the delic-lc via the iom-2000 interface, whereas in figure 5 and figure 6 an iom-2 (gci) interface is used to connect other isdn transceivers. figure 4 delic-lc in s/t and u pn line cards (up to 8 s/t and 16 u pn ) delic-lc peb 20570 pcm 4 x 32 ts iom-2000 signaling up to 2.048 mbit/s up to 4 x s/t 4 x upn up to 4 x s/t 4 x upn 8 x upn memory p infineon c166 vip peb 20590 vip peb 20590 vip peb 20590
peb 20570 peb 20571 introduction data sheet 8 2001-03-19 preliminary figure 5 delic-lc/pb in uk0 line card for 16 subscribers note: in this application delic-pb is also meaningful. 1.4.2 applications for delic-pb figure 6 delic-pb in analog line card for 16 subscribers . . . . . . delic-lc/pb peb 20570 (peb 20571) iom-2 memory p infineon c166 pcm 4 x 32 ts signaling 16 x u k0 afe/ dfe afe/ dfe afe/ dfe afe/ dfe hybrid hybrid hybrid hybrid hybrid hybrid hybrid hybrid delic-pb peb 20571 iom-2 memory p infineon c166 pcm 4 x 32 ts signaling 16 x t/r slicofi-2 slicofi-2 slicofi-2 slicofi-2 hv-slic hv-slic hv-slic iom-2 hv-slic hv-slic hv-slic hv-slic hv-slic
peb 20570 peb 20571 introduction data sheet 9 2001-03-19 preliminary figure 7 delic-pb in small pbx figure 8 delic-pb in 4 port sdsl line card delic-pb peb 20571 iom-2 memory p infineon c166 vip peb 20590 iom-2000 pcm lnc 2 mbit/s for service power supply hv-slic hv-slic hv-slic hv-slic slicofi-2 slicofi-2 central office 32 x t/r 4 x u pn 2 x s 2 x t up to 32 ts socrates socrates socrates socrates c165 memory 3 2 0 1 2 3 voice 1 0 8.192 mbit/s 2.3 mbit/s pcm pcm 8.192 mbit/s iom-2 delic-pb peb 20571 pcm data asic refclk 8.192 mbit/s 4.096 mbit/s
peb 20570 peb 20571 pin description data sheet 10 2001-03-19 preliminary 2 pin description 2.1 pin diagram delic-lc (top view) figure 9 pin configuration delic-lc p-tqfp-100-3 50 49 44 43 42 41 48 47 46 45 40 39 34 33 31 38 37 36 35 76 77 82 83 84 85 78 79 80 81 86 87 92 93 94 95 88 89 90 91 d3 v ss ale wr / r/w rd / ds cs v dd d2 d1 d0 dreqr dreqt iack xclk dsp_frq clk_dsp v ss mode ireq tms jtck lcxd0/lcts0 ltsc0/ lrts0 ltxd0 lrxd0 trst lclk0 v dd v ss dsp_stop stat/ lcts1 dx/ ltxd1 dcl_2000/ lrts1 rxd3/ lcts3 v ss v dd v ss cmd/ lclk1 dr/ lrxd1 delic-lc peb 20570 d4 d7 d5 d6 dcxopd 30 29 28 27 26 32 96 97 98 99 100 scanmo v ss dd1 dd0 du1 du0 l1_clk v ss v dd drdy dcl fsc a4 a3 a2 a1 a6 v ss v dd a5 txd0/ltxd2 v dd v ss txd3/lclk3 pfs txd1/ltxd3 tsc2 txd2/lclk2 tsc3 pdc resind v ssa v ssa v dda v dda refclk v ss v ssa v dd 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 tdo tdi/ scanen v dd rxd2/ lcts2 rxd1/lrxd3 rxd0/lrxd2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1718 19 20 21 22 23 2425 reset clkout v ss v dd a0 v dd clk16-xi clk16-xo v dda tsc1 / lrts3 tsc0 / lrts2
peb 20570 peb 20571 pin description data sheet 11 2001-03-19 preliminary 2.2 pin diagram delic-pb (top view) figure 10 pin configuration delic-pb p-tqfp-100-3 50 49 44 43 42 41 48 47 46 45 40 39 34 33 31 38 37 36 35 76 77 82 83 84 85 78 79 80 81 86 87 92 93 94 95 88 89 90 91 d3 v ss ale wr / r/w rd / ds cs v dd d2 d1 d0 dreqr dreqt iack xclk dsp_frq clk_dsp v ss mode ireq tms jtck lcxd0/lcts0 ltsc0/ lrts0 ltxd0 lrxd0 trst lclk0 v dd v ss dsp_stop stat/ lcxd1/lcts1 dx/ ltxd1 dcl_2000/ ltsc1/lrts1 rxd3/ lcxd3/lcts3 v ss v dd v ss cmd/ lclk1 dr/ lrxd1 delic-pb peb 20571 d4 d7 d5 d6 dcxopd 30 29 28 27 26 32 96 97 98 99 100 scanmo v dd dd1 dd0 du1 du0 l1_clk v ss v dd drdy dcl fsc a4/dack a3 a2 a1 a6 v ss v dd a5 txd0/ltxd2 tsc1 / ltsc3 /lrts3 v dd v ss txd3/lclk3 pfs txd1/ltxd3 tsc2 txd2/lclk2 tsc3 pdc resind v ssa v ssa v dda v dda refclk v ss v ssa v dd 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 tdo tdi/ scanen v dd rxd2/ lcxd2/lcts2 rxd1/lrxd3 rxd0/lrxd2 tsc0 / ltsc2 /lrts2 1 23456 7 8 9 10 11 12 13 14 15 16 1718 19 20 21 22 23 2425 reset clkout v ss v dd a0 v dd clk16-xi clk16-xo v dda
peb 20570 peb 20571 pin description data sheet 12 2001-03-19 preliminary 2.3 pin definitions and functions for delic-lc note: the column ?during reset? refers to the time period that starts with activation of reset input and ends with the deactivation of the resind output. during this period, the delic strap pins (refer to table 19 ) may be driven by external pull- down or pull-up resistors to define delic configuration. if external pull-down or pull-up resistors are not connected to the strap pins, the value of each strap pin during reset will be determined by an internal pull-up or pull-down resistor, according to the default strap value of each pin. the user must ensure that connected circuits do not influence the sampling of the strap pins during reset. the column ?after reset? describes the behavior of every pin, from the deactivation of the resind output until the delic registers are programmed. note: in order to garantee the reset behaviour of every pin please refer to the application hint ? reset behaviour ? on page 287 .
peb 20570 peb 20571 pin description data sheet 13 2001-03-19 preliminary table 1 iom ? -2 interface pins (delic-lc) pin no. symbol in (i) out(o) during reset after reset function 39 fsc o o o frame synchronization clock (8 khz) used for both the iom-2 and the iom- 2000 interface 40 dcl o test- strap (3), (pull-up), refer to table 19 o iom-2 data clock 2.048 mhz or 4.096 mhz 43 dd0 o(od) high z high z data downstream iom-2 interface channel0 44 dd1 o(od) high z high z data downstream iom-2 interface channel1 41 du0 i i i data upstream iom-2 interface channel 0 42 du1 i i i data upstream iom-2 interface channel 1 45 drdy i i i d- channel ready stop/go information for d-channel control on s/t interface in lt-t. affects only iom-2 port 0. drdy = 1 means go drdy = 0 means stop if drdy is not used, this pin has to be connected to ? high ? leve l
peb 20570 peb 20571 pin description data sheet 14 2001-03-19 preliminary table 2 iom-2000 interface / lnc port 1 (delic-lc) pin no. symbol in (i) out (o) during reset after reset function 70 dcl_2000 / lrts1 o o o o iom-2000 data clock 3.072, 6.144 or 12.288 mhz ? request-to-send ? functionality (async mode) 69 dx / ltxd1 o o (od) high z high z data transmit transmits iom-2000 data to vip lnc transmit serial data port 1 (async mode). 68 dr / lrxd1 i i i i data receive receives iom-2000 data from vip lnc receive serial data port 1 (async mode). 67 cmd / lclk1 o i/o high z high z iom-2000 command transmits delic commands to vip. lnc clock port 1. when configured as output may be driven at the following frequencies: 2.048 mhz, 4.096 mhz, 8.192 mhz, 16.384 mhz 64 stat / lcts1 i i i i iom-2000 status receives status information from vip. lnc1 clear to send ? clear-to-send ? functionality (async mode)
peb 20570 peb 20571 pin description data sheet 15 2001-03-19 preliminary . table 3 lnc port 0 (delic-lc) pin no. symbol in (i) out (o) during reset after reset function 62 lrxd0 i i i lnc receive serial data port 0 (hdlc and async mode). 61 ltxd0 o (od) high z high z lnc transmit serial data port 0 (hdlc and async mode). 60 ltsc0 / lrts0 opll- bypass ? strap. pull-up refer to page 38 h lnc0 tristate control / request to send 2 modes per s/w selectable: 1) txd output is valid (hdlc mode). supplies a control signal for an external driver. ( ? low ? when the corresponding txd-output is valid). 2) ? request-to-send ? functionality (async mode) 59 lcxd0 / lcts0 i i i lnc0 collision data / clear to send 2 modes per s/w selectable: 1) collision data (hdlc mode). 2) ? clear-to-send ? functionality (async mode) 56 lclk0 i/o i i lnc clock port 0 when configured as output may be driven at the following frequencies: 2.048 mhz, 4.096 mhz, 8.192 mhz, 16.384 mhz
peb 20570 peb 20571 pin description data sheet 16 2001-03-19 preliminary table 4 microprocessor bus interface pins (delic-lc) pin no. symbol in (i) out (o) during reset after reset function 25 24 23 22 21 18 17 16 d7 d6 d5 d4 d3 d2 d1 d0 i/o the direction of these pins depends on the value of the following pins: cs , rd /ds , wr / r/w and mode data bus when operated in address/data multiplex mode, this bus is used as a multiplexed ad bus. the address pins are externally connected to the ad bus. 38 35 34 33 32 31 30 a6 a5 a4 a3 a2 a1 a0 i i i address bus (bits 6 ... 0) when operated in address/data multiplex mode, this bus is used as a multiplexed ad bus. the data pins are externally connected to the ad bus. 11 dreqr o clock master strap (pull- down), refer to table 19 l strap pin 10 dreqt o emul- ation boot strap (pull- down), refer to table 19 l strap pin 12 cs i i i chip select a "low" on this line selects all registers for read/write operations. 13 wr / r/w i i i write (intel/infineon mode) indicates a write access. read/write (motorola mode) indicates the direction of the data transfer
peb 20570 peb 20571 pin description data sheet 17 2001-03-19 preliminary 14 rd / ds i i i read (intel/infineon mode) indicates a read access. data strobe (motorola mode) during a read cycle, ds indicates that the delic should place valid data on the bus. during a write access, ds indicates that valid data is on the bus. 15 ale i i i address latch enable controls the on-chip address latch in multiplexed bus mode. while ale is ? high ? , the latch is transparent. the falling edge latches the current address. ale is also evaluated to determine the bus mode ( ? low ? =multiplexed, ? high ? =demultiplexed) 7 mode i i i bus mode selection selects the p bus mode ( ? low ? =intel/infineon, ? high ? =motorola) 6ireqo (od) high z (od) high z (od) interrupt request is programmable to push/pull (active high or low) or open- drain. this signal is activated when the delic requests a p interrupt. when operated in open drain mode, multiple interrupt sources may be connected. 5iack i i i interrupt acknowledge 29 reset i i i system reset delic is forced to go into reset state. 89 resind o o o reset indication indicates that the delic is executing a reset. the delic remains in reset state for at least 500 s after the termination of the reset pulse. table 4 microprocessor bus interface pins (delic-lc) (cont ? d) pin no. symbol in (i) out (o) during reset after reset function
peb 20570 peb 20571 pin description data sheet 18 2001-03-19 preliminary table 5 pcm interface ports 0 ... 3 / lnc ports 2 ... 3 (delic-lc) pin no. symbol in (i) out (o) during reset after reset function 87 pfs i/o i i pcm frame synchronization clock. 8 khz/4 khz when input or 8 khz when output. note: when pfs is configured as 4 khz input, pdc configuration is restricted to 2.048 mhz input. 88 pdc i/o i i pcm data clock (input or output) 2.048 mhz, 4.096 mhz, 8.192 mhz, 16.384 mhz 76 rxd0 / lrxd2 i i i i pcm receive data port 0 lnc receive serial data port 2 (async mode) 78 txd0 / ltxd2 o o(od) high z high z pcm transmit data port 0 lnc transmit serial data port 2 async mode) 77 tsc0 / lrts2 o o reset counter bypass ? strap pull-up refer to page 38 h pcm tristate control port 0 supplies a control signal for an external driver ( ? low ? when the corresponding txd- output is valid). lnc2 request to send ? request-to-send ? functionality (async mode) 74 rxd2 / lcts2 i i i i pcm receive data port 2 lnc2 ? clear-to-send ? functionality (async mode) 82 txd2 / lclk2 o i/o weak low weak low pcm transmit data port 2 lnc external clock port 2 when configured as output may be driven at the following frequencies: 2.048 mhz, 4.096 mhz, 8.192 mhz, 16.384 mhz
peb 20570 peb 20571 pin description data sheet 19 2001-03-19 preliminary 81 tsc2 o test(1) strap refer to page 38 h pcm tristate control port 2 supplies a control signal for an external driver ( ? low ? when the corresponding txd- output is valid). 75 rxd1 / lrxd3 i i i i pcm receive data port 1 lnc receive serial data port 3 (async mode) 80 txd1 / ltxd3 o o(od) high z high z pcm transmit data port 1 lnc transmit serial data port 3 (async mode) 79 tsc1 / lrts3 opll power- down strap pull-up refer to page 38 h pcm tristate control port 1 supplies a control signal for an external driver ( ? low ? when the corresponding txd- output is valid). lnc3 request to send ? request-to-send ? functionality (async mode) 71 rxd3 / lcts3 i i i i pcm receive data port 3 lnc3 ? clear-to-send ? functionality (async mode) 86 txd3 / lclk3 o i/o weak low weak low pcm transmit data port 3 lnc external clock port 3 when configured as output may be driven at the following frequencies: 2.048 mhz, 4.096 mhz, 8.192 mhz, 16.384 mhz 83 tsc3 o test(1) strap refer to page 38 h pcm tristate control port 3 supplies a control signal for an external driver ( ? low ? when the corresponding txd output is valid). table 5 pcm interface ports 0 ... 3 / lnc ports 2 ... 3 (delic-lc) (cont ? d) pin no. symbol in (i) out (o) during reset after reset function
peb 20570 peb 20571 pin description data sheet 20 2001-03-19 preliminary table 6 clock generator pins (delic-lc) (additionally to iom/pcm clocks) pin no. symbol in (i) out (o) during reset after reset function 94 clk16-xi i i i 16.384 mhz external crystal input 95 clk16-xo o o o 16.384 mhz external crystal output 1 dcxopd i i i dcxo power down and bypass activating this input powers down the on-chip dcxo pll. the input clk16-xi is used directly as the internal 16.384 mhz clock, and the oscillator and the shaper are bypassed. required for testing; during normal operation this input should be permanently low ( ? 0 ? ). 2 clk_dsp i i i external dsp clock provides a dsp clock other than 61.44 mhz from an external oscillator. 3 dsp_frq i i i dsp operational frequency selection (e.g. for test purpose) 0: the dsp is clocked internally at 61.44 mhz 1: the dsp clock is driven by the clk_dsp input pin 48 l1_clk o o o layer-1 clock 15.36 mhz or 7.68 mhz 28 clkout o o o general purpose clock output 2.048 mhz, 4.096 mhz, 8.192 mhz, 15.36 mhz or 16.384 mhz 4 xclk i i i external reference clock synchronization input from layer-1 ics (8 khz, 512 khz or 1.536 mhz) this pin is connected to the vip ? s refclk output at 1.536 mhz. 90 refclk i/o i i reference clock input: synchronization of delic clock system output: used to drive a fraction of xclk to the system clock master (8 khz or 512 khz programmable)
peb 20570 peb 20571 pin description data sheet 21 2001-03-19 preliminary table 7 power supply pins (delic-lc) pin no. symbol in (i) out (o) during reset after reset function 8 19 26 36 46 57 65 72 84 91 v dd i i i power supply 3.3 v used for core logic and interfaces in pure 3.3 v environment 9 20 27 37 47 49 58 66 73 85 92 v ss i i i digital ground (0 v) 96 99 100 v dda i i i power supply 3.3 v analog logic used for dcxo and pll 93 97 98 v ssa i i i analog ground used for dcxo and pll
peb 20570 peb 20571 pin description data sheet 22 2001-03-19 preliminary table 8 jtag and emulation interface pins (delic-lc) pin no. symbol in (i) out (o) during reset after reset function used for boundary scan according to ieee 1149.1 54 jtck i i i jtag test clock provides the clock for jtag test logic. used also for serial emulation interface. 53 tms i i i test mode select a ? 0 ? to ? 1 ? transition on this pin is required to step through the tap controller state machine. 52 tdi / scanen i i i test data input in the appropriate tap controller state test data or a instruction is shifted in via this line. used also for serial emulation interface. this pin must not be driven to low on the board during reset and operation to ensure functioning of delic scan enable when both scanmo and scanen are asserted, the full-scan tests of delic are activated. not used during normal operation. 51 tdo o o o test data output in the appropriate tap controller state test data or an instruction is shifted out via this line. used also for serial emulation interface. 55 trst i i i test reset provides an asynchronous reset to the tap controller state machine. 63 dsp_stop o boot strap (pull- down) refer to table 19 o dsp stop pin stops external logic during breakpoints. activated when a stop to the dsp is issued.
peb 20570 peb 20571 pin description data sheet 23 2001-03-19 preliminary table 9 test interface pins (delic-lc) pin no. symbol in (i) out (o) during reset after reset function 50 scanmo i i i scan mode if driven to ? 1 ? during device tests, tdi input is used as enable for full scan tests of the delic. scanmo should be tied to gnd during normal operation.
peb 20570 peb 20571 pin description data sheet 24 2001-03-19 preliminary 2.4 pin definitions and functions for delic-pb note: the column ? during reset ? refers to the time period that starts with activation of reset input and ends with the deactivation of the resind output. during this period, the delic strap pins (refer to table 19 ) may be driven by external pull- down or pull-up resistors to define delic configuration. if external pull-down or pull-up resistors are not connected to the strap pins, the value of each strap pin during reset will be determined by an internal pull-up or pull-down resistor, according to the default strap value of each pin. the user must ensure that connected circuits do not influence the sampling of the strap pins during reset. the column ? after reset ? describes the behavior of every pin, from the deactivation of the resind output until the delic registers are programmed. note: in order to garantee the reset behaviour of every pin please refer to the application hint ? reset behaviour ? on page 287 .
peb 20570 peb 20571 pin description data sheet 25 2001-03-19 preliminary table 10 iom ? -2 interface pins (delic-pb) pin no. symbol in (i) out(o) during reset after reset function 39 fsc o o o frame synchronization clock (8 khz) used for both the iom-2 and the iom- 2000 interface 40 dcl o test- strap (3), (pull-up), refer to table 19 o iom-2 data clock 2.048 mhz or 4.096 mhz 43 dd0 o(od) high z high z data downstream iom-2 interface channel0 44 dd1 o(od) high z high z data downstream iom-2 interface channel1 41 du0 i i i data upstream iom-2 interface channel 0 42 du1 i i i data upstream iom-2 interface channel 1 45 drdy i i i d- channel ready stop/go information for d-channel control on s/t interface in lt-t. affects only iom-2 port 0. drdy = 1 means go drdy = 0 means stop if drdy is not used, this pin has to be connected to ? high ? level
peb 20570 peb 20571 pin description data sheet 26 2001-03-19 preliminary table 11 iom-2000 interface / lnc port 1 (delic-pb) pin no. symbol in (i) out (o) during reset after reset function 70 dcl_2000 / ltsc1 / lrts1 o o o o iom-2000 data clock 3.072, 6.144 or 12.288 mhz lnc1 tristate control /request to send 2 modes per s/w selectable: 1) txd output is valid (hdlc mode). supplies a control signal for an external driver. ( ? low ? when the corresponding txd-output is valid). 2) ? request-to-send ? functionality (async mode) 69 dx / ltxd1 o o (od) high z high z data transmit transmits iom-2000 data to vip lnc transmit serial data port 1 (hdlc and async mode). 68 dr / lrxd1 i i i i data receive receives iom-2000 data from vip lnc receive serial data port 1 (hdlc and async mode). 67 cmd / lclk1 o i/o high z high z iom-2000 command transmits delic commands to vip. lnc clock port 1. when configured as output may be driven at the following frequencies: 2.048 mhz, 4.096 mhz, 8.192 mhz, 16.384 mhz 64 stat / lcxd1/ lcts1 i i i i iom-2000 status receives status information from vip. lnc1 collision data / clear to send 1) collision data (hdlc mode). 2) ? clear-to-send ? functionality (async mode)
peb 20570 peb 20571 pin description data sheet 27 2001-03-19 preliminary table 12 lnc port 0 (delic-pb) pin no. symbol in (i) out (o) during reset after reset function 62 lrxd0 i i i lnc receive serial data port 0 (hdlc and async mode). 61 ltxd0 o (od) high z high z lnc transmit serial data port 0 (hdlc and async mode). 60 ltsc0 / lrts0 opll- bypass ? strap. pull-up refer to page 38 h lnc0 tristate control / request to send 2 modes per s/w selectable: 1) txd output is valid (hdlc mode). supplies a control signal for an external driver. ( ? low ? when the corresponding txd-output is valid). 2) ? request-to-send ? functionality (async mode) 59 lcxd0 / lcts0 i i i lnc0 collision data / clear to send 2 modes per s/w selectable: 1) collision data (hdlc mode). 2) ? clear-to-send ? functionality (async mode) 56 lclk0 i/o i i lnc clock port 0 when configured as output may be driven at the following frequencies: 2.048 mhz, 4.096 mhz, 8.192 mhz, 16.384 mhz
peb 20570 peb 20571 pin description data sheet 28 2001-03-19 preliminary table 13 microprocessor bus interface pins (delic-pb) pin no. symbol in (i) out (o) during reset after reset function 25 24 23 22 21 18 17 16 d7 d6 d5 d4 d3 d2 d1 d0 i/o the direction of these pins depends on the value of the following pins: cs , rd /ds , wr / r/w and mode data bus when operated in address/data multiplex mode, this bus is used as a multiplexed ad bus. the address pins are externally connected to the ad bus. 38 35 33 32 31 30 a6 a5 a3 a2 a1 a0 i i i address bus (bits 6 ... 0 except bit 4) when operated in address/data multiplex mode, this bus is used as a multiplexed ad bus. the data pins are externally connected to the ad bus. 34 a4 dack / i i i bit 4 of the address bus/ dma acknowledge in non-dma mode dack /a4 input pin should be connected to a4 of the p address-bus. in dma mode a4 is internally connected to ? 0 ? . 11 dreqr o clock master strap (pull- down), refer to table 19 l dma request for receive direction may be configured to active high or active low (the default is active high) 10 dreqt o emul- ation boot strap (pull- down), refer to table 19 l dma request for transmit direction may be configured to active high or active low (the default is active high)
peb 20570 peb 20571 pin description data sheet 29 2001-03-19 preliminary 12 cs i i i chip select a "low" on this line selects all registers for read/write operations. 13 wr / r/w i i i write (intel/infineon mode) indicates a write access. read/write (motorola mode) indicates the direction of the data transfer 14 rd / ds i i i read (intel/infineon mode) indicates a read access. data strobe (motorola mode) during a read cycle, ds indicates that the delic should place valid data on the bus. during a write access, ds indicates that valid data is on the bus. 15 ale i i i address latch enable controls the on-chip address latch in multiplexed bus mode. while ale is ? high ? , the latch is transparent. the falling edge latches the current address. ale is also evaluated to determine the bus mode ( ? low ? =multiplexed, ? high ? =demultiplexed) 7 mode i i i bus mode selection selects the p bus mode ( ? low ? =intel/infineon, ? high ? =motorola) 6ireqo (od) high z (od) high z (od) interrupt request is programmable to push/pull (active high or low) or open- drain. this signal is activated when the delic requests a p interrupt. when operated in open drain mode, multiple interrupt sources may be connected. 5iack i i i interrupt acknowledge table 13 microprocessor bus interface pins (delic-pb) (cont ? d) pin no. symbol in (i) out (o) during reset after reset function
peb 20570 peb 20571 pin description data sheet 30 2001-03-19 preliminary 29 reset i i i system reset delic is forced to go into reset state. 89 resind o o o reset indication indicates that the delic is executing a reset. the delic remains in reset state for at least 500 s after the termination of the reset pulse. table 13 microprocessor bus interface pins (delic-pb) (cont ? d) pin no. symbol in (i) out (o) during reset after reset function
peb 20570 peb 20571 pin description data sheet 31 2001-03-19 preliminary table 14 pcm interface ports 0 ... 3 / lnc ports 2 ... 3 (delic-pb) pin no. symbol in (i) out (o) during reset after reset function 87 pfs i/o i i pcm frame synchronization clock. 8 khz/4 khz when input or 8 khz when output. note: when pfs is configured as 4 khz input, pdc configuration is restricted to 2.048 mhz input. 88 pdc i/o i i pcm data clock (input or output) 2.048 mhz, 4.096 mhz, 8.192 mhz, 16.384 mhz 76 rxd0 / lrxd2 i i i i pcm receive data port 0 lnc receive serial data port 2 (hdlc and async mode) 78 txd0 / ltxd2 o o(od) high z high z pcm transmit data port 0 lnc transmit serial data port 2 (hdlc and async mode) 77 tsc0 / ltsc2 / lrts2 o o reset counter bypass ? strap pull-up refer to page 38 h pcm tristate control port 0 supplies a control signal for an external driver ( ? low ? when the corresponding txd- output is valid). lnc2 tristate control / request to send 2 modes per s/w selectable: 1) txd output is valid (hdlc mode). supplies a control signal for an external driver. ( ? low ? when the corresponding txd- output is valid). 2) ? request-to-send ? functionality (async mode)
peb 20570 peb 20571 pin description data sheet 32 2001-03-19 preliminary 74 rxd2 / lcxd2/ lcts2 i i i i pcm receive data port 2 lnc2 collision data 2 modes per s/w selectable: 1) collision data (in hdlc mode). 2) ? clear-to-send ? functionality (async mode) 82 txd2 / lclk2 o i/o weak low weak low pcm transmit data port 2 lnc external clock port 2 when configured as output may be driven at the following frequencies: 2.048 mhz, 4.096 mhz, 8.192 mhz, 16.384 mhz 81 tsc2 o test(1) strap refer to page 38 h pcm tristate control port 2 supplies a control signal for an external driver ( ? low ? when the corresponding txd- output is valid). 75 rxd1 / lrxd3 i i i i pcm receive data port 1 lnc receive serial data port 3 (hdlc and async mode) 80 txd1 / ltxd3 o o(od) high z high z pcm transmit data port 1 lnc transmit serial data port 3 (hdlc and async mode) table 14 pcm interface ports 0 ... 3 / lnc ports 2 ... 3 (delic-pb) (cont ? d) pin no. symbol in (i) out (o) during reset after reset function
peb 20570 peb 20571 pin description data sheet 33 2001-03-19 preliminary . 79 tsc1 / ltsc3 / lrts3 opll power- down strap pull-up refer to page 38 h pcm tristate control port 1 supplies a control signal for an external driver ( ? low ? when the corresponding txd- output is valid). lnc3 tristate control / request to send 2 modes per s/w selectable: 1) txd output is valid (hdlc mode). supplies a control signal for an external driver. ( ? low ? when the corresponding txd- output is valid). 2) ? request-to-send ? functionality (async mode) 71 rxd3 / lcxd3/ lcts3 i i i i pcm receive data port 3 lnc3 collision data 2 modes per s/w selectable: 1) collision data (hdlc mode). 2) ? clear-to-send ? functionality (async mode) 86 txd3 / lclk3 o i/o weak low weak low pcm transmit data port 3 lnc external clock port 3 when configured as output may be driven at the following frequencies: 2.048 mhz, 4.096 mhz, 8.192 mhz, 16.384 mhz 83 tsc3 o test(1) strap refer to page 38 h pcm tristate control port 3 supplies a control signal for an external driver ( ? low ? when the corresponding txd output is valid). table 14 pcm interface ports 0 ... 3 / lnc ports 2 ... 3 (delic-pb) (cont ? d) pin no. symbol in (i) out (o) during reset after reset function
peb 20570 peb 20571 pin description data sheet 34 2001-03-19 preliminary table 15 clock generator pins (delic-pb) (additionally to iom/pcm clocks) pin no. symbol in (i) out (o) during reset after reset function 94 clk16-xi i i i 16.384 mhz external crystal input 95 clk16-xo o o o 16.384 mhz external crystal output 1 dcxopd i i i dcxo power down and bypass activating this input powers down the on-chip dcxo pll. the input clk16-xi is used directly as the internal 16.384 mhz clock, and the oscillator and the shaper are bypassed. required for testing; during normal operation this input should be permanently low ( ? 0 ? ). 2 clk_dsp i i i external dsp clock provides a dsp clock other than 61.44 mhz from an external oscillator. 3 dsp_frq i i i dsp operational frequency selection (e.g. for test purpose) 0: the dsp is clocked internally at 61.44 mhz 1: the dsp clock is driven by the clk_dsp input pin 48 l1_clk o o o layer-1 clock 15.36 mhz or 7.68 mhz 28 clkout o o o general purpose clock output 2.048 mhz, 4.096 mhz, 8.192 mhz, 15.36 mhz or 16.384 mhz 4 xclk i i i external reference clock synchronization input from layer-1 ics (8 khz, 512 khz or 1.536 mhz) this pin is connected to the vip ? s refclk output at 1.536 mhz. 90 refclk i/o i i reference clock input: synchronization of delic clock system output: used to drive a fraction of xclk to the system clock master (8 khz or 512 khz programmable)
peb 20570 peb 20571 pin description data sheet 35 2001-03-19 preliminary table 16 power supply pins (delic-pb) pin no. symbol in (i) out (o) during reset after reset function 8 19 26 36 46 49 57 65 72 84 91 v dd i i i power supply 3.3 v used for core logic and interfaces in pure 3.3 v environment 9 20 27 37 47 58 66 73 85 92 v ss i i i digital ground (0 v) 96 99 100 v dda i i i power supply 3.3 v analog logic used for dcxo and pll 93 97 98 v ssa i i i analog ground used for dcxo and pll
peb 20570 peb 20571 pin description data sheet 36 2001-03-19 preliminary table 17 jtag and emulation interface pins (delic-pb) pin no. symbol in (i) out (o) during reset after reset function used for boundary scan according to ieee 1149.1 54 jtck i i i jtag test clock provides the clock for jtag test logic. used also for serial emulation interface. 53 tms i i i test mode select a ? 0 ? to ? 1 ? transition on this pin is required to step through the tap controller state machine. 52 tdi / scanen i i i test data input in the appropriate tap controller state test data or a instruction is shifted in via this line. used also for serial emulation interface. this pin must not be driven to low on the board and should be connected to a pull-up during reset and operation to ensure functioning of delic scan enable when both scanmo and scanen are asserted, the full-scan tests of delic are activated. not used during normal operation. 51 tdo o o o test data output in the appropriate tap controller state test data or an instruction is shifted out via this line. used also for serial emulation interface. 55 trst i i i test reset provides an asynchronous reset to the tap controller state machine. 63 dsp_stop o boot strap (pull- down) refer to table 19 o dsp stop pin stops external logic during breakpoints. activated when a stop to the dsp is issued.
peb 20570 peb 20571 pin description data sheet 37 2001-03-19 preliminary table 18 test interface pins (delic-pb) pin no. symbol in (i) out (o) during reset after reset function 50 scanmo i i i scan mode if driven to ? 1 ? during device tests, tdi input is used as enable for full scan tests of the delic. scanmo should be tied to gnd during normal operation.
peb 20570 peb 20571 pin description data sheet 38 2001-03-19 preliminary 2.5 strap pin definitions table 19 strap pins (evaluated during reset) pin no. strap name strap function dreqr (11) clock master 0: (default) 1: clock slave pdc and pfs are used as inputs. pdc = 2.048 mhz pfs = 4 khz clock master pdc and pfs are used as outputs. pdc = 2.048 mhz pfs = 8 khz dsp_stop (63) boot 0: (default) 1: the dsp starts running from address fffe h , and executes the p boot routine. the dsp starts running directly from address 0000 h . the boot routine is not executed. dcl (40): tsc3 (83): tsc2 (81) test(2) test(1) test(0) 111: (default) regular work mode 101 test mode 1 100 test mode 2 011 test mode 3 010 test mode 4 001 110 test mode 5 undefined dreqt (10) emulation boot 0: (default) 1: after reset the boot-routine loads the program ram via the p-interface (via the general mail-box). after reset the boot-routine loads the program ram via the cdi mail-box (via the jtag interface).
peb 20570 peb 20571 pin description data sheet 39 2001-03-19 preliminary note: when the strap pins are not driven externally during reset, they are driven by internal pull-ups/pull-downs. to reduce power consumption, the internal pull-up/ pull-down resistors are connected only during activated reset input. to ensure the default value of the straps, the pins must not be driven during reset. in case of fixed external pull-up/pull-down, a pull-up/pull-down resistance of 10 k ? +/-10% is recommended. note: because of the internal pull-ups are too weak its recommended to connect any pin used as a strap during reset, to an external pull-up/ pull-down resistor, even if it ? s supposed to be driven to it ? s default strap-value. ltsc (60) pll bypass 0: 1: (default) dsp_clk input pin (the dsp fall-back clock) is used as source for the 61 mhz clock division chain. (only for testing). the pll output is used as the source for the 61 mhz clock division chain. tsc1 (79) pll power down 0: 1:(default) the pll is powered-down. (for iddq tests) the pll is on. tsc0 (77) reset counter bypass 0: 1: (default) the reset-counter is bypassed, thus the internal reset is the filtered reset. the internal reset lasts 1-2 16 mhz cycles after a deactivation of reset . the internal reset lasts 4-5 8 khz cycles (> 500 s) after a deactivation of reset table 19 strap pins (evaluated during reset) (cont ? d)
peb 20570 peb 20571 interface description data sheet 40 2001-03-19 preliminary 3 interface description 3.1 overview of interfaces the delic provides the following system interfaces: iom-2000 interface a new serial layer 1 interface driving up to three vip/ vip8 (v ersatile i sdn p ort, peb 20590/ peb 20591). each vip provides eight 2b+d isdn channels, which can be programmed via iom-2000 to s/t mode or u pn mode. iom-2 (gci) interface two standard iom-2 (gci) ports with eight 2b+d isdn channels each, at a data rate of up to 2 x 2.048 mbit/s. they can be combined to a 4.096 mbit/s highway. pcm interface four standard master/slave pcm interfaces with up to 32 time slots each, at a data rate of up to 4 x 2.048 mbit/s. they can be combined to two 4.096 mbit/s highways or one 8.192 mbit/s highway. additionally, 128 time slots of 256 time slots per 8 khz frame can be transmitted at a rate of 16.384 mbit/s. serial communication interface (ghdlc) an asynchronous serial port supporting hdlc formatted data frames at a data rate of up to 8.192 mbit/s. microprocessor interface a standard 8-bit multiplexed/de-multiplexed p interface, compatible to intel/infineon (e.g. 80386ex, c166) and motorola (e.g. 68340, 801) bus systems. it includes two separate mailboxes, one for normal data transfer, and one for fast dma transfers. jtag boundary scan test interface delic provides a standard test interface according to ieee 1149.1. the 4-bit tap controller has an own reset input. the jtag pins tdi, tdo and jtck may also be used as interface for dsp emulation.
peb 20570 peb 20571 interface description data sheet 41 2001-03-19 preliminary 3.2 iom-2000 interface 3.2.1 overview the iom-2000 interface represents a new concept for connecting isdn layer-1 devices to the delic. the transceiver unit (transiu) and the dsp perform the layer-1 protocol, which enables flexible and efficient operation of the transceiver ic (vip/ vip8). vip/ vip8 supports two types of isdn interfaces: 2-wire (ping-pong) u pn interfaces and 4-wire s/t interfaces. for detailed description please refer to vip/ vip8 data sheet. the iom-2000 interface consists of the following signals: frame synchronization: iom-2000 uses the same 8 khz fsc as the iom-2 ports. data interface: data is transmitted via dx line from delic to vip with dcl_2000 rising edge. data is received via dr line from vip to delic, sampled with dcl_2000 falling edge. command/status interface: configuration and control information of vip ? s layer-1 transceivers is exchanged via cmd and stat lines. data/command clock: data and commands for one vip are transmitted at 3.072 mhz. when delic drives 2 or 3 vips, the transmission rate is increased. reference clock: in lt-t mode, the vip provides a reference clock synchronized to the exchange. in lt-s or u pn mode, delic is always the clock master to vip. figure 11 overview of iom-2000 interface structure (example with one vip) bit 1 bit 0 bit 0 s/t: u pn : dx / dr: data transmit / receive in s/t mode f=3.072 mhz (2 x 8 x 192 kbit/s) data transmit / receive for u pn mode f=3.072 mhz (8 x 384 kbit/s) channel_0 channel_7 fsc dcl_2000 dx cmd dr stat vip delic . . . peb 20590 peb 20570 data ctrl data (peb 20591) (peb 20571)
peb 20570 peb 20571 interface description data sheet 42 2001-03-19 preliminary 3.2.2 iom-2000 frame structure 3.2.2.1 data interface on the isdn line side of the vip, data is ternary coded. since the vip contains logic to detect the level of the signal, only the data value is transferred via iom-2000 to delic. u pn mode in u pn mode, only data is sent via the iom-2000 data interface. s/t mode in s/t mode, data and control information is sent via iom-2000 data interface. every data bit has a control bit associated with it. thus, for each s/t line signal, 2 bits are transferred via dx and dr. bit0 is assigned to the user data, and bit1 carries control information. note: ? data ? is always transmitted prior to ? ctrl ? via dx/dr lines (refer to figure 12 ). table 20 control bits in s/t mode on dr line ctrl (bit1) data (bit0) function 0 0 logical ? 0 ? received on line interface 0 1 logical ? 1 ? received on line interface 1 0 received e-bit = inverted transmitted d-bit (e=d ) (lt-t only) 1 1 f-bit (framing) received; indicates the start of the s frame table 21 control bits in s/t mode on dx line ctrl (bit1) data (bit0) function 0 0 logical ? 0 ? transmitted on line interface 0 1 logical ? 1 ? transmitted on line interface 1 0 not used 1 1 f-bit (framing) transmitted; indicates the start of the s frame
peb 20570 peb 20571 interface description data sheet 43 2001-03-19 preliminary figure 12 iom-2000 data sequence (1 vip with 8 channels) note: 1. data transfer on iom-2000 interface always starts with the msb (related to b channels), whereas cmd and stat bits transfer always starts with lsb (bit 0) of any register 2. all registers follow the intel structure (lsb=2 0 , msb=2 31 ) 3. unused bits are don ? t care ( ? x ? ) 4. the order of reception or transmission of each vip channel is always channel 0 to channel 7. a freely programmable channel assignment of multiple vips on iom-2000 (e.g., ch0 of vip_0, ch1 of vip_0, ch0 of vip_1, ch2 of vip_0,...) is not possible. fsc dcl ch0 bit0 ch1 bit0 (data) dx/dr 125 s 3.072 mhz lt-s mode: u pn mode: ch7 bit 23 (ctrl) f-bit ch0 bit1 ch1 bit0 (ctrl) ch1 bit1 (data) ch7 bit1 (data) ch1,3,5,7 in s mode (lt-s) ch0,2,4,6 in u pn mode ch7 bit0 (data) ch7 bit0 (ctrl) ch0 bit2 data data ctrl ch2 bit2 ch2 bit1 ch2 bit0 ch6 bit37 last bit of u pn frame last bit of lt-s frame
peb 20570 peb 20571 interface description data sheet 44 2001-03-19 preliminary figure 13 iom-2000 data order (3 vips with 24 channels) receive data channel shift in receive direction (dr), data of all iom-2000 channels (ch0...7 if one vip is used, ch0 ... ch23 if three vips are used) is shifted by 2 channels with respect to the transmitted data channels (dx), assuming a start of transmission of ch0 bit0 with the fsc signal. delic is transmitting ch0, while receiving ch2 via dr the same time, etc. dx ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 ch0 dr ch2 ch3 ch4 ch5 ch6 ch7 ch0 ch1 ch2 fsc dcl ch0 bit0 dx/dr 125 s 12.288 mhz f-bit ch24 bit0 (example for 24 channels in u pn mode) ch0 bit37 ch31 bit0 ch23 bit0 not used (don?t care) ch0 bit1 ch24 bit1 ch31 bit1 ch23 bit1 not used (don?t care) ch23 bit37 ch24 bit37 ch31 bit37 not used
peb 20570 peb 20571 interface description data sheet 45 2001-03-19 preliminary 3.2.2.2 command and status interface the cmd and stat lines are the configuration and control interface between delic and vip. the bit streams are partitioned into 32-bit words carrying information dedicated to the vips (cmd_0 / stat_0) followed by information dedicated to the individual channels of the same vip (cmd_0_0 ... cmd_2_7 or stat_0_0 ... stat_2_7). note: as opposed to data, command and status bits are sent channel-wise, starting with channel_0. the transmission clock is the same as the dr/dx data clock. figure 14 iom-2000 cmd/stat handling (1 vip with 8 channels) note: the position of each vip within the iom-2000 frame is programmable by two vip pins (vip_adr0, vip_adr1) to iom-2000 channels 0..7, 8..15 or 16..23. figure 15 iom-2000 command/status sequence (3 vips with 24 channels) fsc dcl cmd s_0c6 s_0c0 s_0c7 stat 0 1 2 31 s_0 status bits of vip_0 status bits of vip_0 channel_7 125 s 3.072 mhz s_0c1 s_0c2 s_0c3 s_0c4 s_0c5 c_0c6 c_0c0 c_0c7 c_0 command bits to vip_0 commands bits to vip_0 channel_7 c_0c1 c_0c2 c_0c3 c_0c4 c_0c5 0 1 2 31 0 1 2 31 0 1 2 31 c_0 ... s_0 ... 3x32-bit empty 3x32-bit empty note: c_0 refers to cmd_0, s_0 to stat_0 c_0c0 refers to cmd_0_0, s_0c0 to stat_0_0 fsc cmd / 125 s vip_0 vip_1 stat vip_0 ch0 ch7 vip_2 vip_1 ch0 ch7 vip_2 ch0 ch7 3 empty 32-bit words 3 empty 32-bit words 3 empty 32-bit words vip_0 ... reserved
peb 20570 peb 20571 interface description data sheet 46 2001-03-19 preliminary commands to vip_n (cmd_n, n = 0 ... 2) initialization and control information for each vip is sent by delic in the following sequence every 125 s via the iom-2000 cmd line (32 cmd_n bits per vip_n): note: all bits are programmed in vip command register (vipcmr0..2). commands to vip_n, channel_m (cmd_n_m, m = 0 ... 7) initialization and control information for each vip channel is sent by delic in the following sequence every 125 s via the iom-2000 cmd line (32 cmd_n_m bits per vip_n channel_m): note: all bits except wr_st, smini(2:0) and msync are programmed in transiu initialization channel command register (ticcr); bits wr_st, smini(2:0) and msync reside in the transiu tx data ram. 31 24 xxx x x x x x 23 16 xxx x x x x x 15 8 x x x x rd_n pllpps sh_fsc delre 70 cmd_n delch(2:0) exref refsel(2:0) wr_n 31 24 cmd_n_m fil smini(2:0) msync exlp plls pd 23 16 x dhen x x pdown loop tx_en pllint 15 8 aac(1:0) bbc(1:0) owin(2:0) mf_en 70 mode(2:0) mosel(1:0) wr_st rd wr
peb 20570 peb 20571 interface description data sheet 47 2001-03-19 preliminary status from vip_n (n = 0 ... 2) status information is sent by each vip in the following sequence via the stat line (32 stat_n bits per vip_n): note: bits delay are read from vip status register (vipstr) in transiu. x = unused status from vip_n, channel_m (m = 0 ... 7) status information is sent by each vip channel in the following sequence via the stat line (32 stat_n_m bits per vip_n channel_m): note: marked bits (*) are not evaluated by the delic, only for vip testing. bits slip, fecv and are directly accessible in the transiu receive data ram. x = unused 31 24 stat_nxxxxxxxx 23 16 xxxxxxxx 15 8 xxxxxxxx 70 delay(7:0) 31 24 stat_n_m x x x x xxxx 23 16 xxxxxxxx 15 8 xxxxxxxx 70 x msync* fcv* fsync* slip fecv rxsta(1:0)
peb 20570 peb 20571 interface description data sheet 48 2001-03-19 preliminary 3.2.3 u pn state machine 3.2.3.1 info structure on the u pn interface signals controlling and indicating the internal state of all u pn transceiver state machines are called infos. four different infos (info 0, 1w, 1, 2, 3, 4) may be sent over the u pn interface, depending on the actual state (synchronized, activated, pending activation,...). when the line is deactivated, info 0 (=no signal on the line) is exchanged by the u pn transceivers at either end of the line. when the line is activated, info 3 (in upstream direction) and info 4 (in downstream direction) are continuously sent. info 3 and 4 contain the transmitted data (b1, b2, d, m). info 1/2 are used for activation and synchronization. table 22 info structure on u pn interface name direction description info 0 upstream downstream no signal on the line info 1w upstream asynchronous wake signal 2 khz burst rate f0001000100010001000101010100010111111 code violation in the framing bit info 1 upstream 4 khz burst rate f000100010001000100010101010001011111m 1) dc code violation in the framing bit info 2 downstream 4 khz burst rate f000100010001000100010101010001011111m 1) code violation in the frame bit info 3 upstream 4 khz burst rate no code violation in the framing bit user data in b, d and m channels b channels scrambled, dc bit 2) optional info 4 downstream 4 khz burst rate no code violation in the framing bit user data in b, d and m channels b channels scrambled, dc bit 2 ) optional
peb 20570 peb 20571 interface description data sheet 49 2001-03-19 preliminary note: 1) the m channel superframe contains: cv code violation [1 kbit/s (once in every fourth frame)] s bits transparent[1 kbit/s channel] t bits transparent[2 kbit/s channel] 2) dc balancing bit; f = framing bit
peb 20570 peb 20571 interface description data sheet 50 2001-03-19 preliminary 3.2.3.2 u pn mode state diagram figure 16 u pn state diagram i3 state ind. cmd. ix iy out p interface upn interface delphi up sm.vsd in reset tim res i0 * pend. deact. tim dr i0 i0 g 4 w ait for dr di dr i0 i0 deactivated di dc i0 i0 pend. act. ar dc arx i2 i1w synchronized uai dc arx, ai i4 i1 activated ai i4 i3 resynchron. rsy dc arx i2 i1 dr dr dr dr res i1w test mode tim tm1 tm2 it1 it2 * tm1 tm2 reset dr dc arx i1 i3 dc arx, ai dr i1, i3 i1 dc dr i0 note : tm2 = send continuous pulses tm1 = send single pulses it1 = test signal invoked by tm1 it2 = test signal invoked by tm2 arx = ar, ar2 uncond. transitions by: res, tm1, tm2, dr arx
peb 20570 peb 20571 interface description data sheet 51 2001-03-19 preliminary the u pn state machine has unconditional and conditional states (refer to figure 16 ): unconditional states reset this state is entered unconditionally after a low appears on the reset pin or after the receipt of command res (software reset). the analog transceiver part is disabled (transmission of info 0) and the u pn interface awake detector is inactive. hence, activation from terminal (te) is not possible. test mode the test signal (it i ) sent to the u pn interface in this state is dependant on the command which originally invoked the state. tm1 causes single alternating pulses to be transmitted (it 1 ); tm2 causes continuous alternating pulses to be transmitted (it 2 ). the burst mode technique normally employed on the u pn interface is suspended in this state and the test signals are transmitted continuously. pending deactivation to access any of the conditional states from any of the above unconditional states, the pending deactivation state must be entered. this occurs after the receipt of a dr command. in this state the awake detector is activated and the state is left only when the line has settled (i.e., info 0 has been detected for 2 ms) or by the command dc. note: although dr is shown as a normal command, it may be seen as an unconditional command. no matter which state the lt is in, the reception of a dr command will always result in the pending deactivation state being entered. conditional states wait for dr this state is entered from the pending deactivation state once info 0 or dc has been identified. from here the line may be either activated, deactivated or a test loop may be entered. deactivated this is the power down state of the physical protocol. the awake detection is active and the device will respond to an info 1w (wake signal) by initiating activation.
peb 20570 peb 20571 interface description data sheet 52 2001-03-19 preliminary pending activation this state results from a request for activation of the line, either from the terminal (info 1w) or from the layer-2 device (ar, ar2). info 2 is then transmitted and the dsp waits for the responding info 1 from the remote device. synchronized this state is reached after synchronization upon the receipt of info 1, i.e. after a maximum of 10 ms. in this state, info 2 is supplied to the remote terminal for synchronization. activated info 1 has a code violation in the framing bit (f-bit), whereas info 3 has none. upon the reception of two frames without a code violation in the f bit, the activated state is entered and info 4 is transmitted. the line is now activated; info 4 is sent to the remote and info 3 is received from the remote. re-synchronization if the recognition of info 3 fails, the receiver will attempt to resynchronize. upon entering this state, info 2 is transmitted. this is similar to the original synchronization procedure in the pending activation state (the indication given to layer 2 is different). however, as before, recognition of info 1 leads to the synchronized state. table 23 u pn state machine codes command abbr. code remark deactivate request dr 0000 initiates a complete deactivation from the exchange side by transmitting info 0 (x) reset res 0001 (x) test mode 1 tm1 0010 transmission of pseudo-ternary pulses at 2 khz frequency (x) test mode 2 tm2 0011 transmission of pseudo-ternary pulses at 192 khz frequency (x) activate request ar 1000 used to start an exchange initiated activation activate request test loop 2 ar2 1010 transmission of info 2, switching of loop 2 (at te), t bit set to one
peb 20570 peb 20571 interface description data sheet 53 2001-03-19 preliminary (x) unconditional commands note: the u pn state machine does support loops but neither c/i commands (arl) nor indications are provided by the mailbox protocol. an loop can be programmed by setting bits ticcmr:loop and ticcmr:exlp for defining it is an internally or externally loop. activate indication = "blocked" ai 1100 transmission of info 4, t bit set to zero deactivate confirmation dc 1111 deactivation acknowledgement, quiescent state indication abbr. code remark timing tim 0000 deactivate state, activation from the line not possible resynchronizing rsy 0100 receiver is not synchronous activate request ar 1000 info 1w received u only activation indication uai 0111 info 1 received, synchronous receiver activate indication ai 1100 receiver synchronous, i.e., activation completed deactivate indication di 1111 info 0 or dc received after deactivation request table 23 u pn state machine codes (cont ? d) command abbr. code remark
peb 20570 peb 20571 interface description data sheet 54 2001-03-19 preliminary 3.2.4 s/t state machine a finite state machine in the delic controls the vip s/t line activation/deactivation procedures and transmission of special pulse patterns. such actions can be initiated by primitives (infos) on the s/t interface or by c/i codes sent via the mailbox. depending on the application mode and the transfer direction, the s/t state machines support different codes in conditional and unconditional states: lt-s mode codes: data downstream = commands: reset, test mode, activate req,.. data upstream = indications: not sync, code violation, timer out,.. states: deactivated, activated, pending, lost framing, test mode the state diagram is shown in figure 17 . lt-t mode codes data upstream = commands: reset, test, activate request,.. data downstream = indications: command x acknowledged,.. conditional states: power up, pending deactivation, synchronized, slip detected,.. the state diagram is shown in figure 18 . unconditional states may be entered from any conditional state and should be left with the command tim: test mode, reset state,.. the s/t layer-1 activation and deactivation procedures implemented in the delic are similar to the ones implemented in the peb 2084, quat-s.
peb 20570 peb 20571 interface description data sheet 55 2001-03-19 preliminary 3.2.4.1 lt-s mode (x) unconditional commands note: the lt-s state machine does not support loops. so neither c/i commands nor indications are provided by the mailbox protocol. a loop can be programmed by setting bits ticcmr:loop and ticcmr:exlp for the respective channel. table 24 lt-s state machine codes command abbr. code remark deactivate request dr 0000 initiates a complete deactivation from the exchange side by transmitting info 0 (x) reset res 0001 (x) test mode 1 tm1 0010 transmission of pseudo-ternary pulses at 2 khz frequency (x) test mode 2 tm2 0011 transmission of pseudo-ternary pulses at 96 khz frequency (x) activate request ar 1000 used to start an exchange initiated activation deactivate confirmation dc 1111 deactivation acknowledgement, quiescent state indication abbr. code remark timing tim 0000 resynchronizing rsy 0100 receiver is not synchronous activate request ar 1000 info 0 received code violation received cvr 1011 after each multi-frame the reception of at least one illegal code violation is indicated four times activate indication ai 1100 receiver synchronous, i.e., activation completed deactivate indication di 1111 timer (32 ms) expired or info 0 received after deactivation request
peb 20570 peb 20571 interface description data sheet 56 2001-03-19 preliminary figure 17 state diagram of lt-s mode state ind. cmd. ix iy out s interface delphi lt-s sm.vsd in reset tim res i0 * test mode tim scp ssp it1 it2 * g4 pend. deact. tim dr i0 i0 g4 wait for dr di dr i0 * g 1 deactivated di dc i0 i0 g2 pend. act. ar dc ar i2 i3 g 3 activated ai dc ar i4 i3 g2 lost framing rsy dc ar i2 i3 res any state dc dr dc dr dr dr dr dr scp ssp ard 1) ard 1) ard 1) i3 i0 dc i0 or 32ms i3 p interface reset note : tm2 = send continuous pulses tm1 = send single pulses it1 = test signal invoked by tm1 it2 = test signal invoked by tm2 any state i3
peb 20570 peb 20571 interface description data sheet 57 2001-03-19 preliminary lt-s mode states g1 deactivated the line interface is not transmitting. there is no signal detected on the s interface, and no activation command is received. g2 pending activation as a result of an info 1 detected on the s line or an ar command, the line interface begins transmitting info 2 and waits for reception of info 3. the timer to supervise reception of info 3 is to be implemented in software. in case of an arl command, loop 2 is closed. g3 activated normal state where info 4 is transmitted to the s interface. the line interface remains in this state as long as neither a deactivation nor a test mode is requested, and the receiver does not loose synchronism. when receiver synchronism is lost, info 2 is sent automatically. after reception of info 3, the transmitter continues sending info 4. g2 lost framing this state is reached when the line interface has lost synchronism in the state g3 activated. g4 pending deactivation this state is triggered by a deactivation request dr. it is an unstable state: status di (state ? g4 wait for dr ? ) is issued by the delic when either info 0 is received, or an internal timer of 32 ms expires. g4 wait for dr final state after a deactivation request. the line interface remains in this state until a response to di (in other words dc) is issued. test mode 1 single alternating pulses are sent on the s interface (2 khz repetition rate). test mode 2 continuous alternating pulses are sent on the s interface (96 khz).
peb 20570 peb 20571 interface description data sheet 58 2001-03-19 preliminary 3.2.4.2 lt-t mode (x) unconditional commands table 25 lt-t mode state machine codes (conditional states) command abbr. code remark timing request tim 0000 requests the line interface to change into power-up state reset res 0001 reset of state machine. transmission of info 0. no reaction to incoming infos (x) test mode 1 tm1 0010 transmission of single pulses on the s/t- interface. the pulses are transmitted with alternating polarity at a frequency of 2khz. (x) test mode 2 tm2 0011 transmission of continuous pulses on the s/t-interface. the pulses are sent with alternating polarity at a rate of 96 khz. tm2 is an unconditional command (x). activate request, priority 8 ar8 1000 activation request with priority 8 for d- channel transmission. this command is used to start a lt-t initiated activation. d- channel priority 8 is the highest priority. it should be used to request signaling information transfer. activate request, priority 10 ar10 1001 activation request with priority 10 for d- channel transmission. this command is used to start a lt-t initiated activation. d- channel priority 10 is a lower priority. it should be used to request packet data transfer. activate request loop arl 1010 activation of loop 3 (x) deactivate indication di 1111 this command forces the line interface into ? f3 power down ? mode.
peb 20570 peb 20571 interface description data sheet 59 2001-03-19 preliminary indication abbr. code remark deactivate request dr 0000 deactivation request if left from f7/f8 reset res 0001 reset acknowledge test mode 1 tm1 0010 tm1 acknowledge test mode 2 tm2 0011 tm2 acknowledge slip detected slip 0011 frame wander larger than +/- 25 s re-synchronization during level detect rsy 0100 signal received, receiver not synchronous power up pu 0111 line interface is powered up activate request ar 1000 info 2 received activate request loop arl 1010 loop 3 closed code violation received cvr 1011 after each multiframe the reception of at least one illegal code violation is indicated four times. activate indication loop ail 1110 loop 3 activated activate indication with priority class 8 ai8 1100 info 4 received, d-channel priority is 8 or 9 activate indication with priority class 10 ai10 1101 info 4 received, d-channel priority is 10 or 11 deactivate confirmation dc 1111 line interface is powered down
peb 20570 peb 20571 interface description data sheet 60 2001-03-19 preliminary figure 18 lt-t mode state diagram (conditional and unconditional states) x 1) dr for transition from f7 or f8 2) ar stands for ar8 or ar10 3) ai stands for ai8 or ai10 4) tmi stands for tm1 or tm2 5) i t 1 = test s i g n a l inv o k ed by i t 1 to1: 16 ms f3 pending deact. dr 1) i0 i0 f3 power down dc di i0 i0 ar i2 tim f3 power up pu tim i0 i0 di tim di i2 di (from f7, f8) tim (from f7, f8) i0 f8 lost framing rsy i0 x i4 i0*to1 i0*to1 ar di i2 f7 activated ai 3) ar 2) i3 i4 f6 synchronized ar i3 i2 x f5 unsynchronized rsy i0 ix i2 i0 f4 pending act. pu ar 2) i1 i0 x i4 i2 i2 i4 ix ix tim i4 i4 i4 tim di tim test mode i tmi 4) tmi 4) it 5) * di reset res res i0 * di tim res res delic reset pin any state tmi 4)
peb 20570 peb 20571 interface description data sheet 61 2001-03-19 preliminary lt-t mode (conditional states) f3 power down this is the deactivated state of the physical protocol. the receive line awake unit is active. f3 power up this state is similar to ? f3 power down ? . the state is invoked by a command tim = ? 0000 ? (or di static low). f3 pending deactivation the line interface reaches this state after receiving info 0 (from states f5 to f8). from this state an activation is only possible from the line (transition ? f3 pending deactivation ? to ? f5 unsynchronized ? ). the power down state may be reached only after receiving di. f4 pending activation activation has been requested from the terminal; info 1 is transmitted; info 0 is still received; ? power up ? is transmitted in the c/i channel. this state is stable: timer t3 (itu i.430) is to be implemented in software. f5/8 unsynchronized at the reception of any signal the vip ceases to transmit info 1, adapts its receiver circuit, and awaits identification of info 2 or info 4. this state is also reached after the line interface has lost synchronism in the states f6 or f7 respectively. f6 synchronized when the vip receives an activation signal (info 2), it responds with info 3 and waits for normal frames (info 4). f7 activated this is the normal active state with the layer 1 protocol activated in both directions. from state ? f6 synchronized ? , state f7 is reached almost 0.5 ms after reception of info 4. f7 slip detected when a slip is detected between the t interface clocking system and the iom-2 interface clocks (phase wander of more than 25 s, data may be disturbed) the line interface enters this state, synchronizing again the internal buffer. after 0.5 ms this state is relinguished.
peb 20570 peb 20571 interface description data sheet 62 2001-03-19 preliminary lt-t mode (unconditional states) the unconditional states should be left with the command tim. test mode 1 single alternating pulses are sent on the t interface (2 khz repetition rate). test mode 2 continuous alternating pulses are sent on the t interface (120 khz). reset state a hardware or software reset (res) forces the line interface to an idle state where the analog components are disabled (transmission of info 0) and the t line awake detector is inactive. restriction in lt-t mode the two first transiu channels out of 24, (i.e. channel_0 and channel_1 in the iom- 2000 frame, referring to vip_0, ch_0 and ch_1) do not work in lt-t mode. in order to have an optimized usage of the lt-channels it is recommended to proceed as follows: if only one vip is used, 8 channels can be applied in lt-t mode by using a dcl_2000 clock of 6.144 mhz and mapping the vip to channel 8..15. if 2 vips are used, up to 16 channels can be applied in lt-t mode by using a dcl_2000 of 12.288 mhz and mapping the vips to channel 8..23. if 3 vips are used up to 22 channels (channel 2..23) may be applied in lt-t mode by using a dcl_2000 of 12.288 mhz.
peb 20570 peb 20571 interface description data sheet 63 2001-03-19 preliminary 3.3 iom ? -2 interface iom-2 is a standardized interface for interchip communication in isdn line cards for digital exchange systems developed by alcatel, siemens, plessey and italtel. the iom-2 interface is a four-wire interface with a bit clock, a frame clock and one data line per direction. it has a flexible data clock. this way, data transmission requirements are optimized for different applications. figure 19 iom ? -2 interface in digital line card mode note: in laundered mode, 8 identical iom-2 subchannels are provided. in analog line cards, a 6-bit c/i channel is available for signaling information. in digital line cards, a dedicated 2-bit d-channel carries the signaling information. 3.3.1 signals / channels fsc frame synchronization clock, 8 khz dcl data clock, up to 4.096 mhz *) dd data downstream, up to 4.096 mbit/s *) du data upstream, up to 4.096 mbit/s *) b1, b2 user data channels, 64 kbit/s each monitor monitor channel d signaling channel, 16 kbit/s c/i command/indication channel mr monitor receive handshake signal mx monitor transmit handshake signal *) for detailed clock and data rates, refer to iomu feature description in chapter 4.3.2
peb 20570 peb 20571 interface description data sheet 64 2001-03-19 preliminary 3.4 p interface the p interface may be operated in different modes. this chapter describes how to configure the delic to each mode. 3.4.1 intel/infineon or motorola mode the processor mode is selected by the mode input pin of the delic. "low" level selects infineon/ intel mode, "high" level selects motorola mode. 3.4.2 de-multiplexed or multiplexed mode in both modes, the a-bus and the d-bus are used in parallel. the a-bus should be connected to the 8 lsbs of ad-bus, coming from the p, also in multiplexed mode. the mode is determined according to the ale input pin. when ale is permanently driven to ? 1 ? , the delic works in de-multiplexed mode. otherwise the delic works in multiplexed mode. the next figure describes the connection of the delic to the address and data buses in the different modes. note: motorola mode is used only with de-multiplexed ad bus. intel/infineon mode may be used with both, multiplexed or de-multiplexed ad bus.
peb 20570 peb 20571 interface description data sheet 65 2001-03-19 preliminary figure 20 delic in multiplexed and in de-multiplexed bus mode note: in both modes only the 7 lsbs of a-bus or ad/bus are connected to the address inputs of the delic. in dma mode dack /a4 input pin is used as dack , and a4 is internally driven to ? 0 ? . in this case a4 of the p a/ad-bus is also not connected to the delic. multiplexed mode p delic ad d a ale ale latch de-multiplexed mode p delic d d a ale latch ? 1 ? a 8 7 8 7
peb 20570 peb 20571 interface description data sheet 66 2001-03-19 preliminary 3.4.3 dma or non-dma mode the internal interface between the on-chip dsp and p is established by two mailboxes: a ? general ? mailbox and a dedicated dma mailbox. the non-dma mode provides the option to combine them together building a double-sized ? general ? mailbox. the delic is configured to dma or non-dma mode by a dedicated bit in the p interface configuration register (mcfg:dma). dma mode the dma mailbox can be accessed only by a dma controller. the dack input pin (together with the rd and wr signals) is used to access the dma mailbox. only the general mailbox can be accessed directly by the p. in dma mode, the pin dack /a4 is used as dack , and a4 of the a-bus or ad-bus coming from the p must not be used as an address line for the delic. in this case a4 is driven internally to ? 0 ? . note: in de-multiplexed mode ad4 should be connected to delic ? s d4input pin. non-dma mode this is the default mode (after reset).the general mailbox and the dma mailbox data registers are concatenated into one double-sized general mailbox, accessible by the p. this broad mailbox consists of a dedicated p mailbox and a dsp mailbox. each of them contains 32 data bytes and 1 command byte. in non-dma mode, dack /a4 is used as a4, in order to include the dma mailbox data registers in the p interface address space. 3.4.4 delic external interrupts the delic contains only one source for an external interrupt - the general mailbox. this interrupt source is the ocmd register of the dsp mailbox. releasing the interrupt is done by the p resetting bit obusy:busy. masking it may be done by resetting the mask bit of the p interface configuration register (mcfg:imask). the interrupt vector issued is the contents of the dsp mailbox command register mcmd. in motorola mode, the interrupt vector is issued upon the first iack pulse, while in infineon/intel mode it is issued upon the second iack pulse. in the latter case, the interrupt vector due to the first iack pulse (if needed), should be issued by an external interrupt controller.
peb 20570 peb 20571 interface description data sheet 67 2001-03-19 preliminary 3.5 jtag test interface the delic provides fully ieee standard 1149.1 compatible boundary scan support to allow cost effective board testing. it consists of: complete boundary scan test test access port controller (tap) five dedicated pins: jtck, tms, tdi, tdo (according to jtag) and an additional trst pin to enable asynchronous resets to the tap controller one 32-bit idcode register 3.5.1 boundary scan test depending on the pin functionality one or two boundary scan cells are provided. when the tap controller is in the appropriate mode data is shifted into/out of the boundary scan via the pins tdi/tdo using a clock of up to 6.25 mhz on pin jtck. the sequence of the delic pins can be taken from the bsdl files. 3.5.2 tap controller the test access port (tap) controller implements the state machine defined in the jtag standard ieee 1149.1. transitions on the pin tms cause the tap controller to perform a state change. the tap controller supports a set of 5 standard instructions: pin type number of boundary scan cells usage input 1 input output 2 output, enable table 26 tap controller instruction codes code instruction function 0000 extest external testing 0001 intest internal testing 0010 sample/preload snap-shot testing 0011 idcode reading id code register 1111 bypass bypass operation
peb 20570 peb 20571 interface description data sheet 68 2001-03-19 preliminary extest is used to verify the board interconnections. when the tap controller is in the state ? update dr ? , all output pins are updated with the falling edge of jtck. when it has entered state ? capture dr ? the levels of all input pins are latched with the rising edge of jtck. the in/out shifting of the scan vectors is typically done using the instruction sample/preload. intest supports internal chip testing. when the tap controller is in the state ? update dr ? , all inputs are updated internally with the falling edge of jtck. when it has entered state ? capture dr ? the levels of all outputs are latched with the rising edge of jtck. the in/out shifting of the scan vectors is typically done using the instruction sample/preload. note: 0011 (idcode) is the default value of the instruction register. sample/preload provides a snap-shot of the pin level during normal operation or is used to either preload (tdi) or shift out (tdo) the boundary scan test vector. both activities are transparent to the system functionality. idcode the 32-bit identification register is serially read out via tdo. it contains the version number (4 bits), the device code (16 bits) and the manufacturer code (11 bits). the lsb is fixed to ? 1 ? . the code for the delic version 3.1 is ? 0100 ? . note: in the state ? test logic reset ? the code ? 0011 ? is loaded into the instruction code register. bypass , a bit entering tdi is shifted to tdo after one jtck clock cycle, e.g. to skip testing of selected ics on a printed circuit board. version device code manufacturer code output 0100 0000 0000 0101 0111 0000 1000 001 1 --> tdo
peb 20570 peb 20571 functional description data sheet 69 2001-03-19 preliminary 4 functional description as the functionality of the delic-pb comprises the functionality of the delic-lc, the following chapter describes the functionality of the delic-pb. the differences between the two chip versions (considering also the firmware) can be seen below: table 27 differences between delic-lc and delic-pb functionality delic-lc delic-pb ghdlc channels (maximum configuration) cha. 0 cha. 0..3 ghdlc maximum data rate 2 mbit/s 8 mbit/s hdlc channels (maximum configuration) cha. 0..23 cha. 0..31 dma interface not available available dma- mailbox not available; it is used to increment the general mailbox can be used for dma operation or as general mailbox number of switching connections (8-bit) 256 variable, limited by dsp-ram multi-bit switching (1-bit, 2-bit, 3-bit...7-bit) no yes dect-synchronization and delay measurement support no yes ? firmware alive indication ? function no yes dsp- run time statistic counter without threshold with threshold dsp-pbx-library for conferencing, tone generation/ detection, dtmf receiver/ generator music on hold 1) 1) these libraries are included in the delic-pb configurator. no yes free programmability of dsp-system no yes
peb 20570 peb 20571 functional description data sheet 70 2001-03-19 preliminary 4.1 functional overview and block diagram figure 21 block diagram upn delic jtag pll 5 p mail box 16 8 16 ... 2 vip/ vip-8 p siemens c166 6 8 x u pn / s/t 0 1 s/t 4 dmac memory 3.3 v 2 x 2.048 mbit/s or 1 x 4.096 mbit/s 3 vip 2 3 subscribers 5 dma mail box interrupt controller different lines: upn or s/t pcm unit ghdlc unit hdlc unit transiu vip 1 vip 0 dsp oak + memory different lines t/r s/t upn uk0 pri layer-1 ics 2x iom /gci iom-2000/ lnc1 refclk 16.384 mhz clocks dsp 61.44 mhz p bus dma interface test int pcm/ lnc2..3 lnc0 3.3 v 5v iom unit mux mux
peb 20570 peb 20571 functional description data sheet 71 2001-03-19 preliminary 4.2 iom-2000 transceiver unit (transiu) 4.2.1 iom-2000 features the transiu controls up to 24 layer-1 channels via up to three vip/ vip8 connected to iom-2000 interface iom-2000 interface: all channels may be programmed in the iom-2000 to: ? u pn interface ? s/t interface in lt-s (subscriber master) or lt-t (trunk slave) mode note: the number of s/t interfaces in vip peb 20590 is limited to 4. therefore it is required to program the iom-2000 correctly to the required mode (refer to table 49 ) clock rates: 3.072 mbit/s (1 vip), 6.144 mbit/s (2 vips) or 12.288 mbit/s (3 vips) data and maintenance bit handling for s/t and u pn interface, including multiframe control and d-channel collision control. scrambling / descrambling (in delic) the b-channel data on the up interface is scrambled in order to ensure that the receiver at the subscriber terminal gets enough pulses for a reliable clock extraction (flat continuous power density spectrum is provided), and to avoid periodic patterns on the line. a descrambler is implemented in the opposite direction to extract the received up data. the scrambling is done according to itu v.27, octat-p and dasl. 4.2.2 iom-2000 initialization channel programming each iom-2000 channel may be configured in the transiu as: u pn mode s/t channel in lt-s mode s/t channel in lt-t mode data rate programming the iom-2000 supports three configurations regarding the number of vips connected via iom-2000: one vip connected at data rate of 3.072 mbit/s: 8 iom-2000 channels at a clock rate of 3.072 mhz (for lt-t mode please refer to page 62 ) two vips connected at data rate of 6.144 mbit/s: 16 iom-2000 channels at a clock rate of 6.144 mhz
peb 20570 peb 20571 functional description data sheet 72 2001-03-19 preliminary three vips connected at data rate of 9.216 mbit/s: 24 iom-2000 channels at a clock rate of 12.288 mhz. (note the difference between clock rate and actual data rate) 4.2.3 initialization of the vip during startup the vip requires 3 frames with the right fsc and dcl_2000 to synchronize to the delic. during this time the vip is not able to detect commands or data from the delic. therefore, the delayed reset signal resind of the delic should be used to reset the vip. 4.2.4 iom-2000 command and status interface all command/status bits used for vip channel programming are divided into one group used only during initialization, and one group used during normal operation. 4.2.4.1 initialization mode command bits the bits of this group are used for vip initialization or in operation modes where an immediate reaction is not required. the initialization group includes command bits and the channel address, stored in register ticcmr. note: the usage of this group of bits is limited in a way that only one channel may be accessed in each frame. in test mode, the command word to vip_n (cmd_n) and to channel_m of vip_n (cmd_n_m) may be read by the delic in the next frame after issuing bits ? rd_n ? or ? rd ? . the vip mirrors the command word exactly as it was received, despite the bits ? wr ? , ? wr_st ? , ? rd ? . the vip status is saved in the transiu initialization status (ticstr) register, which includes status bits and the channel address. note: the commands must not be read during normal operation, since in this case the reporting of the vip status to the delic would not be possible. 4.2.4.2 operational mode command/status bits the bits of this group are used during normal operation, hence they are evaluated in every frame. they include all vip receiver status bits and some of the command bits. the operational mode command/status bits are buffered in the data ram. the vip receiver status bits do not reflect a status change, but the status itself, i.e. the current value of the line interface infos, until the values change. the fecv is only reported to the delic upon changes. 4.2.4.3 command/status transmission the command/status bits are transmitted/received by the transiu at the same rate as data transmission rate, starting with the 8 khz fsc.
peb 20570 peb 20571 functional description data sheet 73 2001-03-19 preliminary transmit direction the command information per vip is prepared by the dsp in the vipcmr0-2 registers the command bits from initialization command group are prepared by the dsp in the ticcmr register for one of the channels transiu operation mode command format in the data ram receive direction the received status per vip is stored in the vipstr0-2 registers if the ? read_status ? command was transmitted in the previous frame for one of the channels, the received status from this channel is saved in the ticstr register together with the 5-bit channel address transiu operation mode status format in the data ram
peb 20570 peb 20571 functional description data sheet 74 2001-03-19 preliminary 4.2.4.4 command and status format in the data ram the operational mode command and status bits usually are served completely by the firmware. so there is no need to set this bits by the user. operational mode command bits in the data ram: address:see memory map 76 5 4 3 2 1 0 data byte 1 data byte 2 data byte 3 x x x smini(2:0) msync wr_st wr_st write command to tst1 bits (s/t, u pn ) 0 = data sent in these bits is invalid 1 = smini(2:0) and msync contain valid data msync multiframe synchronization (lt-t) 0 = vip mirrors the f a -bit 1 = vip stops the f a -bit mirroring (for multiframe synchronization) smini(2:0) state machine initialization (s/t, u pn ) command to vip from the delic layer-1 state machine. depending on the state, the vip may transmit data on the u pn or s/t interface. the vip responds by sending the receiver status bits stat_n_m.rxsta(1:0) to the delic. 000 = info 0 in s/t or u pn 001 = info 1w in u pn 010 = info 1 in lt-t, info 2 in lt-s or u pn 011 = info 3 in lt-t, info 4 in lt-s or u pn 100 = test mode ? send continuous pulses scp ? : ? 1s ? transmitted at 96 khz (u pn ) and at 192 khz s/t) 101 = test mode ? send single pulses ssp ? (at 2 khz burst rate) all other states are reserved
peb 20570 peb 20571 functional description data sheet 75 2001-03-19 preliminary operational mode status bits in the data ram: address:see memory map note: with * marked bits are not evaluated by the delic, only for vip testing. bits slip, fecv and are directly available to the dsp software in the transiu receive data ram. 76543210 data byte 1 data byte 2 data byte 3 x msync fcv fsync slip fecv rxsta(1:0) rxsta(1:0) receiver status change (s/t, u pn ) 00 = receiver is not synchronized to the line; no signal on line (info 0) 01 = level detected on line (any signal) (inf 1 in lt-s mode) 10 = receiver is synchronized to the line, but not activated (info 2 in lt-t mode) 11 = receiver is synchronized and activated (info 4 for lt-t mode info 3 for lt-s and u pn ) fecv far-end code violation (s/t, u pn ) 0 = normal operation 1 = illegal code: fecv according to ansi t1.605 detected (s/t) slip frame slip detected (lt-t) 0 = no frame slip detected 1 = a frame slip of more than 20 s was detected on the lt-t channel fsync * f-bit synchronous (s/t + u pn test mode only!) fcv * code violation in f-bit detected (u pn test mode only!) msync / ld * multiframe synchronous (u pn ), level detected (s/t), test mode!
peb 20570 peb 20571 functional description data sheet 76 2001-03-19 preliminary 4.2.5 u pn mode frame structure the u pn interface uses a ping-pong technique for 2b+d data transmission over the line. u pn is always point-to-point. the frame structure of the data transfer between the exchange (pbx, lt) and the terminal (te) is depicted in figure 22 . the pbx starts a transmission every 250 s (burst repetition period). a frame transmitted by the exchange (pbx) is received by the terminal (te) after a given propagation delay t d . the terminal waits a minimum guard time ( t g = 5.2 s) while the line clears. then a frame is transmitted from the terminal to the pbx. the time between the end of reception of a frame from the te and the beginning of transmission of the next frame by the lt must be greater than the minimum guard time. the guard time in te is always defined with respect to the m-bit.
peb 20570 peb 20571 functional description data sheet 77 2001-03-19 preliminary figure 22 u pn interface frame structure up coding (in vip) the coding technique used on the up interface is a half-bauded ami code (with a 50 % pulse width (refer to figure 23 ). a logical ? 0 ? corresponds to a neutral level, logical ? 1 ? s are coded as alternate positive and negative pulses. code violation (cv) is caused by two successive pulses with the same polarity. the ami coding includes always the data bits going on the up interface in one direction. consequently there is a separate ami coding unit for data from the delic to the vip implemented in the vip, and vice versa. itd00823 lf b1 b2 8 1 8 d 4 8 8 b2 b1 m dc 2) 1 #bits 1 cv t s t cv t s t cv 1) 2) m channel superframe cv = code violation: for superframe synchronization t = transparent channel (2 kbit/s) s = service channel (1 kbit/s) dc balancing bit, only sent after a code violation in the m-bit position and in special configurations. timings: = burst repetition period = 250 = ine delay = 20.8 = guard time = 5.2 t r d t t g s s s maximum minimum g t t d r t d t 99 s lf-framing bit lt te/pt )
peb 20570 peb 20571 functional description data sheet 78 2001-03-19 preliminary figure 23 ami coding on the up interface
peb 20570 peb 20571 functional description data sheet 79 2001-03-19 preliminary 4.2.6 u pn interface the data is received and transmitted at a nominal bit rate of 384 kbit/s. in the first half of the 4 khz frame data is transmitted and ? zeros ? are received, in the second half of the frame ? zeros ? are transmitted and data is received (ping-pong interface). figure 24 handling of u pn frame (one channel) transmit direction since the delic is always master on the up-interface, all transmitted up frames always start with the fsc-2000 (the transmission starts from ch-0.bit-0 which is followed by ch_1.bit_0, ch_2.bit_0,... ch_7.bit_0, ch_1.bit_1, etc.; see also figure 12 ) the lf-bit is generated and inserted at the beginning of the frame. b-channel data prepared by the dsp is scrambled and inserted into the u-frame. d- channel data and m-bit, prepared by the dsp, are inserted into the transmitted up frame by the transiu. receive direction the received frame start is recognized by the lf-bit, which is always logical ? 1 ? (this is the first ? 1 ? received after the fsc_2000). since the received frames start at different points of time (due to the different line delays) the frame start recognition is performed for each channel separately the b-channel data is descrambled the b- and d-channel data and m-bit are stored in the data ram delic vip tx buffer rx buffer dsp transiu 250 s rx: fifos: lf-bit recognition transiu hardware: dc-bit discard dsp software: m-bit handling vip hardware: cv dc tx: iom-2000 hardware: generation of complete up frame dsp software: vip hardware: - for jitter compensation f rx tx dc-bit generation rx fifo state machine sync lf-bit generation b-channel scrambling b-channel descrambling m-bit handling
peb 20570 peb 20571 functional description data sheet 80 2001-03-19 preliminary 4.2.7 u pn framing bit description 4.2.7.1 framing bit (lf-bit) on the u pn interface the framing (lf) bit is always logical ? 1 ? . in the transmit direction the lf-bit is inserted by the transiu at the beginning of every transmitted u pn frame. the vip assumes the start of the u pn frame when detecting the first '1' (lf-bit) in the data stream on iom-2000 dx line together with the 8 khz iom-2000 fsc pulse. this is required due to the 8 khz clock rate of the fsc signal in comparison to the 4 khz frame length in the u pn interface. the code violation in the lf position is generated by the vip when info1 is transmitted, according to the dsp command bits smini(2:0). in the receive direction the first ? 1 ? recognized on the line after ? no signal ? , which is represented by logical ? 0 ? , is treated as the lf-bit. the code violation in the lf-bit position is recognized by the vip when info 2 is received. this information is forwarded to the delic as part of the vip receiver status bits rxsta(1:0). 4.2.7.2 multiframing bit (m-bit) on the u pn interface multiframes are composed of four u pn frames. the multiframe is included at the m-bit position. every fourth m-bit, a code violation indicates the start of a new multiframe. in transmit direction, the vip extracts the multiframe bits out of the iom-2000 data coming from delic and inserts them in the u pn frame at the line side. in receive direction, the vip extracts the multiframe bits out of the data coming from the u pn line and inserts them in the iom-2000 frame to the delic. a multiframe counter in the vip guarantees the timing of the multiframe. it is synchronized (reset) every 20th u pn frame (=every 40th iom-2000 frame) by the command bit ? sh_fsc ? issued by the delic. note: the sh_fsc bit performs the functionality of the short fsc pulse in octat-p and quat-s. t-bit the t-bit received on the u pn line is inserted by the vip in the iom-2000 data receive (dr) line at the multiframe (m-bit) position in every frame; i.e. not only at the usual t-bit position every third frame, but also at the s-bit position and the code violation (cv) position.in transmit direction, the t-bit value is sent in the data stream from the delic to the vip, and passed on transparently to the u pn terminal. the t-bit value may be programmed in delic ? s data ram. it is required e.g. for dect synchronization.
peb 20570 peb 20571 functional description data sheet 81 2001-03-19 preliminary s-bit the s-bit received on the u pn line interface is extracted by the vip out of the data stream, and is logical or ? ed with the detected far-end code violation. the result is sent to the delic as status bit ? fecv ? . in transmit direction, the s-bit value is sent in the data stream from the delic to the vip, and passed on transparently to the u pn terminal. the s-bit value may be programmed in delic ? s data ram. it is required e.g. for switching a digital loop in the terminal. cv-bit the code violation bit received on the line is not transmitted to the delic. 4.2.7.3 dc-balancing bit a dc-balancing bit is inserted by the vip according to the balancing bit control (bbc) bit transmitted to the vip on the command line. in receive direction, the dc balancing bit is received, but not evaluated. 4.2.7.4 u pn mode data format the data is received and transmitted at a nominal bit rate of 384 kbit/s. in the first half of the 4 khz u pn frame data is transmitted and ? zeros ? are received, in the second half of the frame ? zeros ? are transmitted and data is received. scrambling and de-scrambling of the b-channel data is done automatically. the received and transmitted data is stored in the data ram in the following format: u pn mode receive / transmit data format in transmit direction, depending on the multiframe position, the m-bit contains either the t-bit or the s-bit with the following functionality: t-bit: a) d-channel available info to the terminal b) dect synchronization signal s-bit: switches remote loop in terminal device 76543210 b1-channel data b2-channel data d-channel m-bit x xxxx operation mode command/status bits
peb 20570 peb 20571 functional description data sheet 82 2001-03-19 preliminary 4.2.7.5 u pn scrambler/descrambler b-channel data on all u pn channels of the iom-2000 interface is scrambled to give a flat continuous power density spectrum on the line. scrambling is done according to itu-t v.27 with the generator polynomial 1 + x 6 + x 7 , octat-p and dasl. initialization via history ram (hram) the scrambler is activated/deactivated for each u pn channel separately by a dsp write to the history ram address. during initialization the dsp writes a value with '0' in its lsb (other bits are of no importance) to every history ram address associated to an u pn channel that is not to be scrambled, and a value with '1' in its lsb for every u pn channel that must be scrambled. the same values must be written to the descrambler history ram. the hram addresses are: 0x9000 - 0x9017 (scrambler u pn channel 0..23) 0x9020 - 0x9037 (descrambler u pn channel 0..23) for example, in order to activate scrambling and descrambling for channel number 3, the dsp must execute two write operations as follows: write "xxxxxxxxxxxxxxx1" to address 0x9002 write "xxxxxxxxxxxxxxx1" to address 0x9022 these writes are executed only when the scrambler is in idle mode, i.e. value 0x0003 was written by the oak to address 0xd010. note: the hram setting is handled by the dsp according to the scrambler mode register (address 0xd010). 4.2.8 dect synchronization for u pn - interface for dect systems the delic supports synchronization of the different radio base stations (rbs). synchronization is controlled by the dsp via the t-bit in the u pn -frame.
peb 20570 peb 20571 functional description data sheet 83 2001-03-19 preliminary 4.2.9 s/t interface frame structure the s/t interface establishes a direct link between the vip and connected subscriber terminals or to the central office. it consists of two pairs of copper wires: one for the transmit and one for the receive direction. direct access to the vip ? s s/t interface by the delic is not possible. 2b+d user data as well as s/q channel information can be inserted and extracted via the iom-2000 interface. framing bits are generated and transmitted to the vip by the delic. transmission over the s/t interface is performed at a rate of 192 kbit/s. pseudo-ternary coding with 100 % pulse width is used. 144 kbit/s are used for user data (36 bits of b1+b2+d) and 48 kbit/s (12 bits) are used for framing, s/q and maintenance information. for each s/t channel, the vip uses two symmetrical, differential outputs (sx1, sx2) and two symmetrical, differential inputs (sr1, sr2). these signals are coupled via external circuitry and two transformers onto the 4 wire s/t interface. the nominal pulse amplitude on the s/t interface is 750 mv (zero-peak). s/t coding the following figure illustrates the code used. a binary one is represented by no line signal (0 v). binary zeros are coded with alternating positive and negative pulses with two exceptions: the first binary zero following the framing balance bit is of the same polarity as the framing-balancing bit, and the f-bit is always at positive level (required code violations). figure 25 s/t interface line code (without code violation) a standard s/t frame consists of 48 bits. in the direction te nt the frame is transmitted with a 2-bit offset. for details on the framing rules please refer to itu i.430. the following figure illustrates the standard frame structure for both directions (nt te and te nt) with all framing and maintenance bits.
peb 20570 peb 20571 functional description data sheet 84 2001-03-19 preliminary figure 26 frame structure at reference points s and t (itu i.430) in lt-t configurations, the delic receives the reference clock from the central office via the iom-2000 refclk line. the vip selects the reference clock source via two multiplexers. the source may be either one of the 8 vip channels operated in lt-t mode or the clkin pin when driving multiple cascaded vips on the iom-2000. ? f framing bit f = (0b) code violation, identifies a new frame (always positive pulse) ? l. d.c. balancing bit l. = (0b) number of binary zeros sent after the last l. bit was odd ? d d-channel data bit signaling data specified by user ? e d-channel echo bit e = d if d-channel is not blocked, otherwise e=d . (zeros always overwrite ones ? f a auxiliary framing bit see section 6.3 in itu i.430 ? nn = ? b1 b1-channel data bit user data ? b2 b2-channel data bit user data ? a activation bit a = (0b) info 2 transmitted a = (1b) info 4 transmitted ? s s-channel data bit s 1 or s 2 channel data ? m multiframing bit m = (1b) start of new multi-frame f a
peb 20570 peb 20571 functional description data sheet 85 2001-03-19 preliminary figure 27 reference clock selection for cascaded vips on iom-2000 note: a change in the reference clock source must not result in a fsc jump greater than the difference of the clock phase before and after the change, which otherwise would result in big frame slips. vip_0 vip_1 delic refclk_0 1.536 mhz dr vip_2 lt-t ch_0 ch_7 ch_0 ch_7 ch_0 ch_7 clkin_0 reference clock refclk clkin ch_0 ch_7 vip_n refsel exref clkin_1 clkin_2 refclk_1 refclk_2 xclk
peb 20570 peb 20571 functional description data sheet 86 2001-03-19 preliminary 4.2.9.1 lt-s mode figure 28 handling of so frame in lt-s mode (one channel) transmit direction since the delic is master in the lt-s mode, all transmitted frames always start with the fsc-2000 (the transmission starts from ch-0.bit-0 which is followed by ch_1.bit_0, ch_2.bit_0,... ch_7.bit_0, ch_0.bit_1, etc.; see also figure 12 ) the f-, l- and n-bits are generated and inserted into the s/t frame the information about d-channel availability is transmitted at the e-bit position the b- and d-channel data, a-, f a -, m- and s-bits are prepared by the dsp and inserted into transmitted s/t frame by the iom-2000 receive direction the received frame start is recognized by the f-bit. since the received frames start at different points of time (due to the different line delays) the frame start recognition is performed for each channel separately the received l-bits are discarded the b- and d-channel data bits and f a -bit are arranged in the data ram vip tx buffer rx buffer dsp transiu 250 s rx: f-bit & cv detection e-bit mirroring inversion of data (b1, b2, d) f a -bit handling (4-bit q-channel) transiu hardware: l-bit discard dsp software: vip hardware: q-fifo s-fifo f,l tx: f-bit & cv generation inversion of data (b1, b2, d) s-bit handling (8-bit service ch.) transiu hardware: generation of complete s frame dsp software: vip hardware: inv inv rx tx m f a multiframe generation rx fifos fifos: -for jitter etc. sync info 2,4 recognition f-, l-, n-bit generation f-bit recognition control of e-bit mirroring control of e-bit mirroring delic f
peb 20570 peb 20571 functional description data sheet 87 2001-03-19 preliminary d-echo bit generation in lt-s mode in the lt-s mode, the last received d-bit has to be reflected in the next available e-bit (e=d). if there are no hdlc controllers available, the d-channel is blocked (e=d is transmitted). since it is necessary to meet the itu requirement to react immediately (i.e., even when line delays of several bits have occurred) upon the reception of a d-bit by issuing the e-bit, the e-bit has to be inserted by the vip. the information about the d- channel availability is provided to the vip in the e-bit data field. table 28 d-echo bit information about the availability of hdlc controllers is provided to the iom-2000 by the dsp. figure 29 d-echo bit generation bit0 (data) bit1(control) 0 0 the transmitted e-bit is equal to the received d-bit 1 0 the transmitted e-bit is equal to the inverted received d-bit vip e / d logic d d delic dsp e e dx dr
peb 20570 peb 20571 functional description data sheet 88 2001-03-19 preliminary 4.2.9.2 lt-t mode figure 30 handling of so frame in lt-t mode (one channel) receive direction the received frame start is recognized by the f-bit. since the delic is a slave in the lt-t mode, the received frames may start at any point of time, and the frame start recognition is performed for each channel independently. the received l- and n-bits are discarded the received e-bit is compared with the last transmitted d-bit ? if collision is detected on the d-channel it is reported to the dsp the received b- and d-channel data bits, a-, f a -, m- and s-bits as well as the information about collision detected on the d-channel are stored in the data ram. transmit direction according to itu.430, the 2-bit delay between received and transmitted frames must be guaranteed at the te (i.e., this delay must be controlled by the vip). because of the vip delay in both receive and transmit directions (this delay is the same for all lt- t lines and is always constant (tbd during vip design)), the transiu starts the lt- t frame transmission before the f-bit of received frame is recognized. the f- and l-bits are generated and inserted into the s/t frame vip tx buffer rx buffer dsp transiu 250 s rx: inversion of data (b1, b2, d) f a -bit check every 5th frame transiu hardware: n- and l-bit discard dsp software: m-bit & s-channel handling a-bit handling (info 2 or 4) vip hardware: s-fifo q-fifo f,l tx: f-bit & cv generation inversion of data (b1, b2, d) transiu hardware: generation of complete s frame dsp software: vip hardware: inv inv rx fifos f-bit & cv detection fifos: - for jitter etc. e-/d-bit handling, e / d rx tx e e-bit collision detection d f a sync q-channel handling f-, l-bit generation collision detection delic d-channel priority handling
peb 20570 peb 20571 functional description data sheet 89 2001-03-19 preliminary the b-channel data is prepared by the dsp in the data ram and inserted into the downstream frame by the transiu if collision was detected on the d-channel, the data transmission on this channel is blocked by the transiu and the 1 ? s are sent on the d-channel instead of the data from the data ram until the data sending is enabled by the dsp the b- and d-channel data bits and f a -bit are prepared by the dsp in the data ram in the same format as lt-s received frames collision detection on d-channel in lt-t mode the collision is detected on the d-channel when the received e-bit is not equal to the last transmitted d-bit. the transiu compares the e-bit with the d-bit when the collision is detected, the transiu indicates collision to the dsp, and starts to send 1 ? s on the d-channel. the priority mechanism is implemented in software. the transiu provides the following information to the dsp (2 bits per lt-t ? configured channel, which are stored in the data ram, see ? lt-t mode receive data format ? on page 94 . ? collision detection on d-channel (cl-bit): ? 0 ? ? no collision in the d-channel, ? 1 ? ? collision was detected in the d-channel. ? collision detection bit number: ? 0 ? ? collision was detected in the 1-st bit of the frame, ? 1 ? ? collision was detected in the 2-nd bit of the frame. the dsp counts to 8/9 (higher priority) or 10/11 (lower priority) and enables the transiu to transmit the data on the d-channel at the end of counting. the transiu stops d-channel blocking immediately, all relevant data (end of idle or start of the flag) is already prepared by the dsp in the data ram. if the new collision was detected by the transiu during the current collision, the dsp resets the priority mechanism counters and starts counting from the beginning.
peb 20570 peb 20571 functional description data sheet 90 2001-03-19 preliminary figure 31 collision detection in the lt-t mode 4.2.10 s/t mode control and framing bits on iom-2000 4.2.10.1 framing bit (f-bit) the framing (f) bit is recognized on the transiu interface, when both data and control bits are equal to ? 1 ? . in the transmit direction the data and control bits are inserted by the transiu at the beginning of every transmitted frame; in the receive direction the framing bit is used for frame start recognition. 4.2.10.2 multiframing bits in s/t interface, the multiframe includes 20 s/t frames. the start of a multiframe is indicated by the m- and f a -bits (the m-bit is set to ? 1 ? in every 20 th frame, the f a -bit is set to ? 1 ? in every 5 th frame). the s/q channel provides the additional capability for data exchange between lt-s and te or between the central office (co) and the lt-t at the multiframe level. in the lt-s- to-te direction the s-channel (s-bit in s/t frame) is used. in the opposite direction (te to lt-s) the data is transferred on the q-channel. the q-bits are defined to be the bits in the f a bit position of every 5 th frame. the q-bit position is identified by f a = ? 1 ? in the te to lt-s direction. a multiframe is provided for structuring the q-bits in groups of four (q1-q4). the q- and s-channel coding with respect to the frame number is shown in table 29 . delic dsp hdlcu e / d logic d e transiu collision status data buffer
peb 20570 peb 20571 functional description data sheet 91 2001-03-19 preliminary figure 32 s/q channel assignment vip te co lt-s lt-t s s q q delic iom-2000
peb 20570 peb 20571 functional description data sheet 92 2001-03-19 preliminary note: 1.only frame positions (within the 20-frame multiframe) that carry s- or q-channel information are shown here 2.the q- and s-bits, which are not used, are set to ? 1 ? . on the iom-2000 interface, the s/t multiframe information is included in the dx/dr data stream (transparent to the vip). the values of the multiframe are controlled by the dsp software in the delic. when multiframe synchronization is not achieved or lost, the vip mirrors the received f a bits. once the multiframe synchronization is established, the dsp sends the multiframe synchronization command to the vip (msync bit). upon reception of the msync, the vip stops mirroring the f a -bit. 4.2.10.3 f a /n bit in the transmit direction the f a /n bit pair is coded in such a way that n is the binary opposite of the f a . the f a bit is equal to binary ? 0 ? , except every 5 th frame when it is set to ? 1 ? , which indicates the q-bit position to the te. the receive direction, the f a bit positions represent the q-channel. table 29 s/t mode multiframe bit positions frame number lt-s to te or co to lt-t, f a bit position lt-s to te or co to lt-t, m-bit lt-s to te or co to lt-t, s-bit te to lt-s or lt-t to co f a bit position 111s11q1 200s210 610s12q2 700s220 11 1 0 s13 q3 12 0 0 s23 0 16 1 0 s14 q4 17 0 0 s24 0 ... ... ... ... ...
peb 20570 peb 20571 functional description data sheet 93 2001-03-19 preliminary 4.2.10.4 dc-balancing bit (l-bit) in transmit (downstream) direction the l-bit is generated in compliance with itu-t i.430: a balance bit is ? 0 ? if the number of 0 ? s following the previous balance bit is odd. a balance bit is ? 1 ? if the number of 0 ? s following the previous balance bit is even. it is inserted by the vip according to the balancing bit control (bbc) bit sent to the vip by the delic via the cmd line. in receive (upstream) direction, the dc balancing bit is received on the line, but not evaluated. 4.2.11 iom-2000 data interface data processing and frame handling in the transiu is fully dsp controlled. serial data received and transmitted on the transiu interface is arranged in the shift receive ram and shift transmit ram. the dsp processed bytes are stored in the transiu current buffer. every 8 khz frame the transiu and dsp current buffers are switched. 4.2.11.1 s/t mode data format data is received/transmitted at a nominal rate of 192 kbit/s. each s/t data bit is translated into two bits on iom-2000: data (bit0) and control (bit1). lt-s mode transmit data format lt-s mode receive data format 76543210 b1-channel data b2-channel data d-channel x f a ms x x operation mode command/status bits 76543210 b1 - channel data b2 - channel data d-channel f a xxxxx operation mode command/status bits
peb 20570 peb 20571 functional description data sheet 94 2001-03-19 preliminary lt-t mode transmit data format lt-t mode receive data format 4.2.12 test loop the delic/vip allows to set up internal as well as remote loops for testing by programming registers ticcmr and tutrl. note: please refer also to the application note ? test loops in the vip ? . 76543210 b1-channel data b2-channel data d-channel f a xxxxx operation mode command/status bits 76543210 b1-channel data b2-channel data d-channel x f a m s cbn cdi operation mode command/status bits cbn collision detection bit number 0 = collision was detected in the first d-bit of the s-frame half (corresponds to the second echo-bit of the frame half) 1 = collision was detected in the second d-bit of the s-frame half (corresponds to the first echo-bit of the frame half) cdi collision detection indication 0 = no collision in d-channel 1 = collision in d-channel detected
peb 20570 peb 20571 functional description data sheet 95 2001-03-19 preliminary 4.3 iom-2 unit 4.3.1 iomu features the iomu provides the dsp access to incoming time slots from the iom-2 interface. features dsp access for switching of b1 and b2 data to the pcmu, transiu and iomu (providing a constant switching delay of two 8 khz frames) dsp access for extracting d-channel information dsp access for control of iom-2 command/indication (c/i) and monitor channel information interface configuration two iom-2 ports providing up to 16 iom-2 channels (up to 16 isdn or 32 analog subscribers) available data rate modes: ? one port of 384 kbit/s each (1 x 6 time slots per frame) ? one port of 768 kbit/s each (1 x 12 time slots per frame) ? two ports of 2.048 mbit/s each (2 x 32 time slots per frame) ? one port of 4.096 mbit/s (1 x 64 time slots per frame) single or double data rate clock selectable for data rates up to data rates up to 2.048 m bit/s programmable tri-state control for each port and channel (=4 time slots) push-pull or open-drain configuration drdy signal for d-channel control when connected to quat-s peb 2084
peb 20570 peb 20571 functional description data sheet 96 2001-03-19 preliminary 4.3.2 iomu functional and operational description figure 33 iomu integration in delic 4.3.2.1 frame-wise buffer swapping the main task of the iomu is the serial-to-parallel conversion of incoming iom-2 data to a parallel data format which is directly read by the dsp. this access is required for the dsp to perform switching of b-channels, extraction of d-channels, and layer-1 control via the iom-2 c/i and monitor channels. the data conversion in the iomu is done by frame-wise swapping based on a circular buffer structure. during each 8 khz frame, one buffer is assigned to the iomu (i-buffer), and the other one to the dsp (d-buffer). at the end of every frame, the buffers are swapped. 4.3.2.2 dsp inaccessible buffer (i-buffer) logical structure the logical partitioning of each frame buffer into input and output blocks is determined according to the requested data rate as shown in the table below. delic iomu pcmu hdlcu iom-2000 dsp iom-2 interface dd0 du0 b1 b2 m d,c/i d.c/i m b2 b1 dd1 du1 b1 b2 m d,c/i d.c/i m b2 b1 pcm interface iom-2000 interface switching switching drdy clocks fsc dcl
peb 20570 peb 20571 functional description data sheet 97 2001-03-19 preliminary 4.3.2.3 dsp access to the d-buffer the d-buffer is mapped to a fixed dsp address space. every dsp access to the d-buffer space is directed automatically to the appropriate sub-buffer. e.g. the address of time slot 5 is 0x8005 in receive and 0x8045 in transmit direction. . table 30 i-buffer logical memory mapping data rate input blocks output blocks in0 in1 out0 out1 2 x 2.048 mbit/s 00 h - 1f h 20 h - 3f h 40 h - 5f h 60 h - 7f h 1 x 384 kbit/s 00 h - 05 h -- 40 h - 05 h -- 1 x 768 kbit/s 00 h - 0b h -- 40 h - 4b h -- 1 x 4.096 mbit/s 00 h - 3f h -- 40 h - 7f h -- table 31 d-buffer address space data-rate mode d-buffer in0 in1 out0 out1 2 x 32 time slots/frame 8000 h - 801f h 8020 h - 803f h 8040 h - 805f h 8060 h - 807f h 1 x 6 time slots/frame 8000 h - 8005 h - 8040 h - 8045 h - 1 x 12 time slots/frame 8000 h - 800b h - 8040 h - 804b h - 1 x 64 time slots/frame 8000 h - 803f h - 8040 h - 807f h -
peb 20570 peb 20571 functional description data sheet 98 2001-03-19 preliminary 4.3.2.4 circular buffer architecture figure 34 iomu frame-wise circular-buffer architecture the following description analyses the frame-wise circular-buffering scheme, on a frame to frame basis. assume that during frame n, buffer-0 is used as i-buffer, while buffer-1 is used as d- buffer. the iomu stores the incoming frame-n time-slots in buffer-0 input-blocks and drives outward the frame n time-slots which are read from buffer-0 output-blocks. at the same time the dsp reads the time-slots that arrived during frame n-1 (the previous frame) from buffer-1 input-blocks and prepares the time-slots to be driven outward in the next frame, frame n+1, in buffer-1 output blocks. delic iomu dsp i-buffer in0 in1 d-buffer frame-wise buffer swapping du1 serial parallel parallel serial belongs to the iomu belongs to the dsp du0 out0 out1 in0 in1 out0 out1 dd1 dd0 every frame
peb 20570 peb 20571 functional description data sheet 99 2001-03-19 preliminary a buffer-swapping takes place at the end of frame-n, as at the end of any other frame. this means that during frame-n+1, buffer-1 is used as i-buffer, while buffer-0 is used as d-buffer. during this frame the iomu handles the incoming and outgoing frames n+1, and writes/reads the time-slots to/from buffer-1 input/output blocks. in parallel, the dsp handles buffer-0 input and output blocks. it reads the frame-n up-stream time-slots from the input-blocks and prepares the frame-n+2 down-stream time-slots in the output blocks. the buffer-swapping at the end of frame-n+1 re-assigns buffer-0 as the i-buffer and buffer-1 as the d-buffer (exactly as in frame-n). figure 35 illustrates the frame-wise circular-buffering scheme during two consecutive frames, as described in the previous example. figure 35 the circular-buffer during two consecutive frames frame n frame n+1 buffer 0 used as i-buffer buffer 1 used as d-buffer in0 in1 out0 out1 in0 in1 out0 out1 frame n written by the iomu, from frame n read by the iomu, to dd frame n-1 read by the dsp frame n+1 written by the dsp buffer 0 used as d-buffer buffer 1 used as i-buffer in0 in1 out0 out1 in0 in1 out0 out1 du frame n+1 written by the iomu, from frame n+1 read by the iomu, to dd du frame n read by the dsp frame n+2 written by the dsp swap
peb 20570 peb 20571 functional description data sheet 100 2001-03-19 preliminary 4.3.2.5 iom-2 interface data rate modes the iomu may support different serial data rates of the iom-2 interface: 384 kbit/s (6 time slots per frame) 768 kbit/s (12 time slots per frame) 2.048 mbit/s (32 time slots per frame = 8 iom-2 channels per frame) 4.096 mbit/s (64 time slots per frame = 16 iom-2 channels per frame) the iomu circular buffer may handle up to 64 time slots per frame. thus, when in 4.096 mbit/s mode, only iom-2 port 0 is used. in this case iom-2 port 1 remains in idle mode, i.e. the dd1 output pin is tri-stated. the iomu meets the iom-2 interface timing specifications as described below. single data rate dcl mode serial transmission via dd0/dd1 with every dcl rising edge sampling of the incoming serial data (du0/du1) with every dcl falling edge sampling fsc with every dcl falling edge. sampling of fsc = 1 after sampling of fsc = 0 is considered to be the start of a frame. double data rate dcl mode two dcl cycles per bit (the bits are aligned to the frame start) serial transmission via du0/1 with every second dcl rising edge. sampling of incoming serial data (dd0/1) with the second dcl falling edge of each bit. sampling of fsc every dcl falling edge. sampling of fsc = 1 after sampling of fsc = 0, is considered to be the start of a new frame. figure 36 shows the iom-2 interface timing with single and double rate dcl. table 32 dcl frequency in different iom-2 modes single/double rate dcl mode iom-2 mode 1x384 kbit/s 1x768 kbit/s 2x2.048 mbit/s 1x4.096 mbit/s single 384 khz 768 khz 2.048 mhz 4.096 mhz double 768 khz 1536 khz 4.096 mhz -
peb 20570 peb 20571 functional description data sheet 101 2001-03-19 preliminary figure 36 iom-2 interface timing in single/double clock mode 4.3.2.6 iomu serial data processing the iomu serial data processing is according to the iom-2 specifications. incoming serial data is converted into parallel bytes, and stored in the i-buffer input blocks. the sequence for every time slot received is from msb (bit 7) to lsb (bit 0). transmission is performed in the opposite direction, from msb (bit 7) to lsb (bit 0). 4.3.2.7 iomu parallel data processing the data read from the iomu frame buffers by the dsp always reside in the low byte of the 16-bit word. the high byte of the read word is driven by the 8-bit iomu data prefix register (idpr). the data prefix is used to accelerate the a-/-law to linear conversions (refer to chapter 4.5 ). note: any octet written by the dsp to any location in the iomu frame buffers should reside in the low byte (8 lsb). the high byte of the written word is ? don ? t care ? . fsc dcl dd0/1 ts31 bit0 ts0 bit7 ts0 bit6 ts0 bit5 ts0 bit4 ts0 bit3 ts0 bit2 ts0 bit1 ts0 bit0 ts1 bit7 du0/1 ts31 bit0 ts0 bit7 ts0 bit6 ts0 bit5 ts0 bit4 ts0 bit3 ts0 bit2 ts0 bit1 ts0 bit0 ts1 bit7 single data rate dcl fsc dcl dd0/1 du0/1 = upstream sampling double data rate dcl frame start = fsc sampling ts31 bit0 ts0 bit7 ts0 bit6 ts0 bit5 ts0 bit4 ts0 bit7 frame start ts0 bit6 ts0 bit5 ts0 bit4 ts31 bit0
peb 20570 peb 20571 functional description data sheet 102 2001-03-19 preliminary 4.3.2.8 iom-2 push-pull and open-drain modes the iom-2 ports can be configured to push-pull or open-drain modes by a dedicated bit in the iomu control register. when programmed to open-drain, dd0/dd1 is tri- stated when a ? 1 ? is supposed to be transmitted, or during a time slot quadruplet with the associated tri-state register bit set. in both cases the external pull-up resistor, which is used when working in open-drain mode, will ? pull ? the value to ? 1 ? . note: when the iomu is programmed to 1x 64 time slots per frame mode, dd1 is tri- stated, independently of the iom-2 interface push-pull or open-drain mode. figure 37 iom-2 interface open-drain mode figure 38 iom-2 interface push-pull mode iomu delic dd0 dd1 itsr mux mux downstream0 data downstream1 data iomu delic dd0 dd1 itsr mux mux downstream0 data downstream1 data
peb 20570 peb 20571 functional description data sheet 103 2001-03-19 preliminary 4.3.2.9 support of drdy signal from quat-s the drdy input is used when connecting an infineon quat-s transceiver to the delic via the iom-2 interface. it is driven by the quat-s to inform the delic when a d- channel is occupied by another s-interface device. the iomu supports the synchronous drdy mode, i.e. the quat-s is operated in lt-t mode. in this mode, the drdy signal is valid only during the d-channels. drdy = ? 0 ? means stop (abort hdlc message), and drdy = ? 1 ? means go. figure 39 drdy signal behavior iomu drdy support features: sampling drdy only once every d-channel at the first bit. sampling with the first dcl falling edge (in single data-rate dcl mode) or with the second falling dcl edge (in double data-rate dcl mode), refer to figure 40 . drdy support via iom-2 port 0 only (with a constant delay of one 8 khz frame) the status of the drdy line can be read from register idrdyr figure 40 drdy sampling timing note: if drdy is not used, drdy has to be set to ? high ? . du0 fsc iom-2 ch 7 d b1 b2 mon iom-2 ch 0 d b1 b2 mon iom-2 ch 1 d b1 b2 mon iom-2 ch 2 d b1 b2 mon iom-2 ch 3 d b1 b2 mon drdy go go stop stop stop = not valid du0 d0 d1 first bit of a d-channel second bit of a d-channel single data-rate dcl drdy valid double data-rate dcl sample point of drdy in single data-rate dcl mode sample point of drdy in double data-rate dcl mode
peb 20570 peb 20571 functional description data sheet 104 2001-03-19 preliminary 4.4 pcm unit pcm interface features the pcmu enables the dsp to control the 4 pcm ports. the dsp accesses the incoming pcm time slots, and prepares the outgoing pcm time slots. in general, the pcmu enables the dsp to switch time slots from pcmu to pcmu, iomu and transiu. the basic structure and programming model of the pcmu is similar to the iomu. however, the pcmu provides the double capacity of the iomu. thus it may handle up to 4 pcm ports and an overall of 128 time slots per frame in the receive direction and 128 time slots per frame in the transmit direction. the following pcmu data rate modes are available: four streams of 2.048 mbit/s each (single and double clock) two streams of 4.096 mbit/s each (single and double clock) one stream of 8.192 mbit/s (single and double clock) one stream of 16.384 mbit/s (single clock). it is programmable, whether the first or the second 128 time slots of the 8 khz frame are handled in the pcmu. note: other data rates, e.g. 3 x 8.192 mbit/s are possible by a firmware change. this is realized by assigning dsp data memory to the pcmu. tri-state control is performed via pins tsc n, programmable per time slot and port.
peb 20570 peb 20571 functional description data sheet 105 2001-03-19 preliminary 4.4.1 pcmu functional and operational description figure 41 pcmu integration in delic the pcm-unit signals share port pins with the ghdlc-unit. a multiplexer controlled by register muxctrl allows to define the required functionality. 4.4.1.1 frame-wise buffer swapping the main task of the pcmu is the serial-to-parallel conversion of incoming data to a parallel data format (and vice versa) which is directly read by the dsp. this access is required for the dsp to perform switching. the data conversion in the pcmu is done by frame-wise swapping based on a circular buffer structure (see also figure 35 ). during each 8 khz frame one buffer is assigned to the pcmu (i-buffer) and the other one to the dsp (d-buffer). at the end of every frame the buffers are swapped. 4.4.1.2 dsp inaccessible buffer (i-buffer) the logical partitioning of each frame buffer into input and output blocks is determined according to the requested data rate as shown in the table below. pcm unit ghdlc unit hdlc unit transiu dsp oak + memory rxd0, txd0, tsc0 iom unit mux pcm interface rxd1, txd1, tsc1 rxd2, txd2 rxd3, txd3 pdc, pfs tsc2 tsc3
peb 20570 peb 20571 functional description data sheet 106 2001-03-19 preliminary note: in 1 x 16.384 mbit/s only the first half of the frame is saved in the buffer 4.4.1.3 dsp accessible buffer (d-buffer) the d-buffer is mapped to a fixed dsp address space. every dsp access to the d-buffer space is directed automatically to the appropriate sub-buffer. e.g. time slot 32 can be accessed at address 0xa020 in receive and 0xa0a0 in transmit direction. table 33 i-buffer logical memory mapping of input buffers data rate input blocks in0 in1 in2 in3 related port rxd0 rxd1 rxd2 rxd3 4 x 2.048 mbit/s 00 h - 1f h 20 h - 3f h 40 h - 5f h 60 h - 7f h 2 x 4.096 mbit/s 00 h - 3f h - 40h - 7fh - 1 x 8.192 mbit/s 00 h - 7f h --- 1 x 16.384 mbit/s 00 h - 7f h --- table 34 i-buffer logical memory mapping of output buffers data rate output buffer blocks out0 out1 out2 out3 related port txd0 txd1 txd2 txd3 4 x 2.048 mbit/s 80 h - 9f h a0 h - bf h c0 h - df h e0 h - ff h 2 x 4.096 mbit/s 80 h - bf h - c0h - ffh - 1 x 8.192 mbit/s 80 h - ff h --- 1 x 16.384 mbit/s 80 h -ff h --- table 35 dsp access to d-buffer input blocks data rate input buffer blocks in0 in1 in2 in3 related port rxd0 rxd1 rxd2 rxd3 4 x 2.048 mbit/s a000 h - a01f h a020 h - a03f h a040 h - a05f h a060 h - a07f h 2 x 4.096 mbit/s a000 h - a03f h - a040h - a07fh - 1 x 8.192 mbit/s a000 h - a07f h -- - 1 x 16.384 mbit/s a000 h - a07f h -- -
peb 20570 peb 20571 functional description data sheet 107 2001-03-19 preliminary note: in 1 x 16.384 mbit/s only the first half of the frame is saved in the buffer. 4.4.1.4 pcmu interface data rate modes the pcmu may support different serial data rates: up to 4 ports with 2048 mbit/s (32 time slots per frame) up to 2 ports with 4.096 mbit/s (64 time slots per frame) 1 port with 8.196 mbit/s (128 time slots per frame) 1 port with 16.384 mbit/s (only 128 time slots of the frame are supported) the pcmu circular buffer may handle up to 128 time slots per frame. thus, when e.g. configured in 4.096 mbit/s mode, only pcm port 0 and 2 are used. in this case pcm port 1 and 3 remain in idle mode, i.e. the txd1, txd3 output pins are tri-stated. for the data rate modes up to 8.192 mbit/s, single rate data clock (pdc) or double rate data clock may be selected. for 16.384 mhz mode only single clock is supported. single data rate pdc mode serial transmission via txdn with every dcl rising edge sampling of the incoming serial data (rxdn) with every pdc falling edge sampling pfs with every pdc falling edge. sampling of pfs = 1 after sampling of pfs = 0 is considered to be the start of a frame. double data rate pdc mode two pdc cycles per bit (the bits are aligned to the frame start) serial transmission via txdn with every second pdc rising edge. sampling of incoming serial data (rxdn) with the second pdc falling edge of each bit. sampling of pfs every pdc falling edge. sampling of pfs = 1 after sampling of pfs = 0, is considered to be the start of a new frame. table 36 dsp access to d-buffer output blocks data rate output buffer blocks out0 out1 out2 out3 related port txd0 txd1 txd2 txd3 4 x 2.048 mbit/s a080 h - a09f h a0a0 h - a0bf h a0c0 h - a0df h a0e0 h - a0ff h 2 x 4.096 mbit/s a080 h - a0bf h -a0c0h - a0ffh - 1 x 8.192 mbit/s a080 h - a0ff h -- - 1 x 16.384 mbit/s a080 h - a0ff h -- -
peb 20570 peb 20571 functional description data sheet 108 2001-03-19 preliminary figure 36 shows the pcm interface timing with single and double rate pdc. figure 42 iom-2 interface timing in single/double clock mode 4.4.1.5 pcmu serial data processing the incoming serial data is converted into parallel bytes, and stored in the i-buffer input blocks. the sequence for every time slot received is from msb (bit 7) to lsb (bit 0). transmission is performed from msb (bit 7) to lsb (bit 0). 4.4.1.6 pcmu parallel data processing the data read from the pcmu frame buffers by the dsp always reside in the low byte of the 16-bit word. the high byte of the read word is driven by the 8-bit pcmu data prefix register (pdpr). the data prefix is used to accelerate the a-/-law to linear conversions (refer to chapter 4.5 ). any octet written by the dsp to any location in the pcmu frame buffers should reside in the low byte (8 lsb). the high byte of the written word is ? don ? t care ? . pfs pdc txd ts31 bit0 ts0 bit7 ts0 bit6 ts0 bit5 ts0 bit4 ts0 bit3 ts0 bit2 ts0 bit1 ts0 bit0 ts1 bit7 rxd ts31 bit0 ts0 bit7 ts0 bit6 ts0 bit5 ts0 bit4 ts0 bit3 ts0 bit2 ts0 bit1 ts0 bit0 ts1 bit7 single data rate pdc pfs pdc txd rxd = data sampling double data rate pdc frame start = pfs sampling ts31 bit0 ts0 bit7 ts0 bit6 ts0 bit5 ts0 bit4 ts0 bit7 frame start ts0 bit6 ts0 bit5 ts0 bit4 ts31 bit0
peb 20570 peb 20571 functional description data sheet 109 2001-03-19 preliminary 4.4.1.7 pcmu tri-state control logic there are eight 16-bit tri-state control registers in the pcmu. each bit determines whether its associated time slot is valid or invalid. '0' = the controlled time slot is invalid '1' = the controlled time slot is valid the tri-state bits control the data transmit pins txd0 - txd3. a special set/reset write method is used for updating the tri-state control registers. every tri-state control register is mapped to 2 addresses: the first is used for set operation, the second for reset operation. both addresses may be used for read operation. set operation: this operation is executed during dsp write access to the set address of one of the tsc registers. the bits in the tsc register are set to '1' according to the bits in the written word. the other bits maintain their value. reset operation: this operation is executed during dsp write access to the reset address of one of the tsc registers. the bits in the tsc register are reset to '0' according to the bits in the written word. the other bits maintain their value. the tri-state control registers (pts0-7) can be accessed by the dsp. every bit of them controls the tsc signal of one of the 4 pcm ports, for one time slot. the time slot and the port controlled by every bit depend on the data rate mode. in 1 x 256 ts/frame, it depends also on the selected half of the frame. each tsc signals controls directly its respective txd port, and is also driven outward via the corresponding tscn output pin. for the 4 x 32 time slot per frame mode, the next table depicts which port is controlled by each tsc register, and during which time slot. bit 0 of each tsc register controls the first time slot of the listed time slot range, bit 1 controls the second one etc. in 2 x 64 time slot per frame mode, only pcm ports 0 and 2 are used. tsc1 and tsc3 are permanently '0' (all time slots are invalid). table 37 pcm tsc in 4 x 32 ts mode (4 x 2 mbit/s) time slots tsc0 tsc1 tsc2 tsc3 0..15 ptsc0 ptsc2 ptsc4 ptsc6 16..31 ptsc1 ptsc3 ptsc5 ptsc7 table 38 pcm tsc in 2 x 64 ts mode (2 x 4mbit/s) time slots tsc0 tsc1 tsc2 tsc3 0..15 ptsc0 inactive ptsc4 inactive 16..31 ptsc1 inactive ptsc5 inactive 32..47 ptsc2 inactive ptsc6 inactive 48..63 ptsc3 inactive ptsc7 inactive
peb 20570 peb 20571 functional description data sheet 110 2001-03-19 preliminary in 1 x 128 time slot per frame mode, only pcm port 0 is used. tsc1, tsc2 and tsc3 are permanently '0' (all time slots are invalid). in 1 x 256 time slot per frame mode, only one half of the frame is used. all tsc pins are permanently '0' during the other half of the frame. note: the same structure applies to the 256 ts per frame (first frame half) mode, except that all time slots (0..127) are transmitted in the first half of the 8 khz frame. note: concerning the behavior of pcm output driver also see ? pcm output driver anomaly ? on page 286 table 39 pcm tsc in 1 x 128 ts (1 x 8 mbit/s) and 1 x 256 ts (1 x 16 mbit/s) (1 st half) mode time slots tsc0 tsc1 tsc2 tsc3 0..15 ptsc0 inactive inactive inactive 16..31 ptsc1 inactive inactive inactive 32..47 ptsc2 inactive inactive inactive 48..63 ptsc3 inactive inactive inactive 64..79 ptsc4 inactive inactive inactive 80..95 ptsc5 inactive inactive inactive 96..111 ptsc6 inactive inactive inactive 112..127 ptsc7 inactive inactive inactive table 40 pcm tsc in 1 x 256 ts (1 x 16 mbit/s) (2 nd half) mode time slots tsc0 tsc1 tsc2 tsc3 0..127 inactive inactive inactive inactive 128..143 ptsc0 inactive inactive inactive 144..159 ptsc1 inactive inactive inactive 160..175 ptsc2 inactive inactive inactive 176..191 ptsc3 inactive inactive inactive 192..207 ptsc4 inactive inactive inactive 208..223 ptsc5 inactive inactive inactive 224..239 ptsc6 inactive inactive inactive 240..255 ptsc7 inactive inactive inactive
peb 20570 peb 20571 functional description data sheet 111 2001-03-19 preliminary 4.5 a-/-law conversion unit the a-/-law unit performs a bi-directional conversion between a linear representation of voice data and its companded representation (according to a-law or -law ). the conversion is applicable on all b-channels via iom-2, iom-2000 or pcm. figure 43 a/-law unit integration dsp iomu pcmu iom-2000 s w i t c h i n g conversion 256 256 16 a -law to linear -law to linear linear to a/-law logic circuit rom a/-law unit input ff output ff
peb 20570 peb 20571 functional description data sheet 112 2001-03-19 preliminary a-/-law to linear conversion the conversion is done via a 512 x 16 rom table. the low 256 bytes translate the a-law value into linear, while the high 256 words translate the -law to linear. the dsp issues a read cycle, in which the 8 msbs of the 16-bit address represent the rom table address, and the 8 lsbs are the actual value which is to be converted. the converted linear value is the contents read from the rom. note that no wait states are required for this direction of conversion. a-law values in the rom are stored in the 13 msbs. the 3 lsbs are always '0'. the - law values in the rom are stored in the 14 msbs. the 2 lsbs are always '0'. linear to a-/-law conversion the conversion is done by dedicated hardware. the dsp programs the control register to perform either a-law or -law conversion. the linear value is written into the input register (amir), and the a-law or -law value is read from the output register (amor). note that this is only possible one cycle later.
peb 20570 peb 20571 functional description data sheet 113 2001-03-19 preliminary 4.6 hdlc unit 4.6.1 hdlc overview high-level data link control (hdlc) is a most common protocol in the data link layer, layer 2 of the osi model. signalling protocols labd and lapb are based on hdlc and its framing structure: opening flag, address field, control field, data field, crc, closing flag, interframe timefill. hdlc uses a zero insertion/deletion process (bit-stuffing) to ensure that a data bit pattern matching the delimiter flag (01111110 = 7eh) does not occur in a field between the starting and the closing flag. the hdlc frame is synchronous. an address field is needed to carry the frame's destination address because the frame can be sent to different systems. an address field can be 8, or 16 bits long, depending on the data link layer protocol. lapb uses an 8-bit address, lapd 16-bit address. the length of the data in the data field depends on the frame protocol. error control is implemented by appending a cyclic redundancy check (crc) to the frame, which is 16 bits long. the multichannel hdlc controller within the delic consists of two parts: a hardware block (hdlc unit) and a dedicated on-chip processor (oak dsp). the processor handles the hdlcu by writing/reading signalling data and reacts on slow events by software. the following table shows the main hdlc features and the responsible unit for its handling: note: the multichannel hdlc unit is not connected to any delic pin. hdlc features hdlc unit processor flag detection and generation x zero insertion/deletion (bit stuffing) x 16-bit crc-ccitt generation and checking x time slot assignment (2- or 16-bit) x programmable flags between successive frames x x flexible address handling x flexible buffers management (per frame) x separate interrupts for frames and buffers (rx and tx) x flag/abort/idle generation and detection x x detection of non-octet aligned frames x automatic retransmission in case of collision x
peb 20570 peb 20571 functional description data sheet 114 2001-03-19 preliminary the hdlc automatically recognizes hdlc frames with the following interframe time fill combinations: n consecutive flags (n = 1, 2, 3,.. ; n = 1 is called shared flag, if the closing flag of one frame is the opening flag of the next frame. n > 1 is also called unshared flag mode.) m "ones" between the closing flag and the opening flag (even when m = 1 to 5) corrupted flag between the closing flag and the opening flag the hdlcu may process up to 32 full-duplex hdlc channels in parallel. as it is controlled by the dsp, it is very flexible. the hdlcu includes 32 receive input buffers, 32 receive output buffers, 32 transmit input buffers and 32 transmit output buffers, some hdlc protocol processing logic and a command ram. figure 44 hdlcu general block diagram figure 44 shows the hdlcu structure. each buffer, except the transmit output buffer, is 1 byte small, hence one byte is assigned to each hdlc channel per direction. the transmit output buffer is 2 bytes as it also contains a 7-bit status vector assigned to the channel. receive output buffer transmit input buffer receive input buffer transmit output buffer 32 channels 32 channels 32 channels 32 channels processing internal command ram dsp control dsp data double buffer dsp data double buffer encoded decoded 32x8 32x16 32x8 32x8 32x8 dsp d-buffer* dsp d-buffer* processing internal * frame-buffers of the iomu, pcmu or iom-2000 that belong to the dsp during the present frame
peb 20570 peb 20571 functional description data sheet 115 2001-03-19 preliminary the dsp assigns each time slot used for transmitting an hdlc message to a different address in the receive/transmit input buffers. the hdlcu decodes/encodes the time slots into the corresponding addresses in the receive/transmit output buffers. during every frame, two hdlcu activities are performed: 1. dsp access to the hdlcu 2. hdlcu encoding/decoding at the beginning of a frame the dsp checks if the hdlcu is busy (hhold = ? 0 ? ). note: the dsp may only access the buffers and command ram when dspctrl = ? 1 ? . in the receive direction the dsp places hdlc message time slots to be processed from the d-buffers into the receive input buffer. processed message time slot octets may be read by the dsp from the receive output buffer. in the transmit direction the dsp places hdlc message time slots to be processed in the transmit input buffer. processed time slots may be read from the transmit output buffer and placed into the d-buffer of the iomu, pcmu or transiu from which they will be transmitted during the next frame. 4.6.2 hdlcu operation 4.6.2.1 initialization of the hdlcu the dsp first resets the receive and transmit mechanisms of all hdlc channels. 1. the dsp requests the external controller for hdlcu setup. 2. the dsp sets the bit dspctrl to ? 1 ? . 3. the dsp resets the receive mechanism and transmit mechanism of a channel by setting the recres flag of its command vector to ? 1 ? and inserting an abort command. the dsp also writes the setup of the hdlcu. 4. the dsp sets dspctrl to ? 0 ? . 5. when the hdlcu finishes processing (hhold = ? 1 ? ), the hdlcu is initialized and is ready for use. 4.6.2.2 transmitting a message the dsp must place a start transmission command at the appropriate address in the command ram. if crc encoding is required, the dsp must set bit 1 to ? 1 ? in the command vector. after the first flag has been transmitted, the hdlc starts to transmit the message. in shared flag mode the hdlcu starts transmitting the message in the frame adjacent to the reception of the start transmission command. note: messages with zero byte data content are not supported.
peb 20570 peb 20571 functional description data sheet 116 2001-03-19 preliminary 4.6.2.3 ending a transmission when placing the last octet of the message into the transmit input buffer, the dsp places an end transmission command in place of the start transmission command without changing the crc bit. if crc encoding is required, the crc vector will be transmitted bit by bit after the octet of the message, and then a flag will be transmitted. if crc encoding is not required, a flag will be transmitted directly after the last octet of the message. 4.6.2.4 aborting a transmission in order to abort transmission of a message over a dedicated channel, the dsp places an abort command in the appropriate address in the command ram. the message being transmitted over the channel is aborted and ? ones ? are transmitted over the channel instead (even in shared flag mode). 4.6.2.5 dsp access to the hdlcu buffers reading a channel from the receive output buffer and writing to a channel in the transmit input buffer is done according to the channel status vector and according to the empty and full procedures as shown below: empty procedure if the empty flag of a channel is set by the hdlcu to ? 1 ? , then move a new time slot to be transmitted from the pipe to the transmit input buffer. if the pipe is empty change the pipe page and ask for the next 8 bytes of data from the external controller by means of dma or transfer ready indication. note: the b-channel buffer may be emptied within a single frame, while it takes at least 4 frames to empty a d-channel buffer. full procedure if the full flag of a channel is set by the hdlcu to ? 1 ? then the dsp moves the time slot from the receive output buffer into the double buffer. if the pipe is full change the pipe page and transfer the next 8 bytes of data to the external controller by means of dma or transfer ready indication. note: the b-channel buffer may be filled within a single frame, while a d-channel buffer will take at least 4 frames to fill. 4.6.3 functionality the multichannel hdlc controller can be assigned to any timeslot on any time-division multiplexing (tdm) port: iom-2, pcm and transiu.
peb 20570 peb 20571 functional description data sheet 117 2001-03-19 preliminary in receive direction, the processor fetches the d-channel (16 kbit/s signalling) or the b- channel (64 kbit/s) from the assigned timeslot and writes it into the corresponding channel register of the hdlc unit. after the hdlc unit encoded the data (e.g. performed bit stuffing), the processor reads ready data and stores it in the receive buffer in on-chip memory. the data flow is shown in the following figure. figure 45 hdlc data flow in receive direction the receive input and receive output buffers within the hdlcu are 1 byte per hdlc channel. the main rx buffer in dsp ram is 2 x 8-byte large per hdlc channel (in the delic-lc version). dsp data memory dp ram s/p hdlc channel_n ("o", flag, crc) p iom-2 / pcm dsp receive input buffer receive output buffer 1. rx buffer page 1 e.g. 8 byte 2. hdlc-rx hdlc unit maibox 3. dp ram with iom-2 or pcm structure delic b1 b2 mon m d c/i rx buffer page 2 e.g. 8 byte b1 b2 mon m d c/i
peb 20570 peb 20571 functional description data sheet 118 2001-03-19 preliminary the processor handles the hdlcu (tasks 1) during every iom frame, i.e. every 125 s. if a 16-kbit/s channel is handled, the task 2 is performed about every 4th to 5th frame (4 x 2-bit writing to the hdlcu minus ? 0-detection ? => 8-bit output). at the beginning of a frame, the dsp checks if the hdlcu is busy (hhold = ? 0 ? ). the dsp may only access the buffers and command ram when dspctrl = ? 1 ? . in transmit direction, the dsp writes data 8-bit wise into the transmit input buffers, reads the processed data from the transmit output buffers and places the coded data into the assigned destination time slot like in the following example: 2-bit wise writing into the d-channel of an iom-2 interface of the iom unit, or into the transiu in case of transiu interface, 8-bit wise writing into a signalling channel of the pcm highway by writing into the pcm unit. in general, the hdlc controller can handle all 32 hdlc channels at different data rates using any tdm channel: e.g. 16 kbit/s for d-channel signalling 64 kbit/s for b-channel signalling 8 kbit/s for proprietary signalling (only pb version) 256 kbit/s for data transfer in transparent mode.
peb 20570 peb 20571 functional description data sheet 119 2001-03-19 preliminary 4.7 ghdlc unit 4.7.1 ghdlc overview messages are transceived serially, bit by bit over the line and undergo encoding/ decoding according to the hdlc protocol. a received message is collected bit by bit from the line and stored as octets in the receive buffer and read by the dsp. a transmitted message which is placed by the dsp as octets in the transmit buffer, is transmitted bit by bit over the line. the ghdlc (general hdlc) controller works similar to hdlcu (refer to ? hdlc overview ? on page 113 ). main features/differences: it has its own physical interface with the following signal lines: lrxd, ltxd, ltsc, lcxd, lclk, it works at a speed of up to 8.192 mbit/s it supports also multi master bus it may work independently from the internal clocking (fsc, pdc,..) using an external clock the receive/transmit buffer in the ghdlc are 2 x 32 bytes large, respectively like the hdlc controller, the ghdlc controller consists also of two parts: a hardware block (ghdlc unit for fast events) and a processor (oak dsp). data from the serial input line (lrxd) is processed and stored in the receive buffer which is to be read by the dsp. transmit data is placed by the dsp in the transmit buffer, is processed by hardware and transmitted over the serial line (ltxd). . figure 46 data processing in the ghdlc 4.7.2 ghdlc general modes of operation each ghdlc channel has three main modes of operation: hdlc mode: in this mode flag-recognition/insertion and zero deletion/addition are performed. crc decoding/encoding may be performed. receive buffer transmit buffer receive processing transmit processing data in from line data out to line bit by bit double buffer double buffer bit by bit dsp dsp command vector set-up vectors status and interrupt vector lrxd ltxd
peb 20570 peb 20571 functional description data sheet 120 2001-03-19 preliminary transparent mode: no hdlc framing exists. in the receive direction everything on the line is automatically passed to the buffer. each time the buffer is filled an interrupt to the dsp is generated. asynchronous mode: this mode is used with request to send/ clear to send handshaking. in this mode data is transmitted over a channel at a very slow rate of up to 300 baud and controlled directly by the dsp. rts /cts hand-shaking in point to point configuration the lcxd and ltxd are used for cts and rts handshaking. a transmission request is indicated by outputting a logical ? 0 ? on the request to send output (rts). after having received the permission to transmit (cts), the hdlc starts data transmission. if permission to transmit is withdrawn in the course of transmission, the frame is aborted and an idle is sent. 4.7.3 external configuration and handshaking in bus mode the ghdlc is connected to the following delic interface lines: figure 47 ghdlc interface lines serial data is transceived over the lrxd/ltxd lines. the line clock can be driven by an external ghdlc device or can be generated internally by the pcm clocking path. the selected internal clock is also driven outward via lclk. 4.7.3.1 external tri-state in point-to-multi-point mode ltsc is the external tri-state control line. when ltsc is high ltxd is disabled and in high impedance state. when ltsc is low, ltxd may take on values 0 or 1 when in push pull mode, 0 or high impedance when in open drain mode. 4.7.3.2 arbitration between several ghdlcs arbitration between several ghdlcs can be done in two ways: polling collision detection ghdlc ltxd ltsc lrxd lcxd / cts / rts lclk
peb 20570 peb 20571 functional description data sheet 121 2001-03-19 preliminary polling means that the dsp is polled to see if it has anything to send by way of a frame which is actually a question. the ghdlc simply receives this frame and passes it on to the dsp like any other. note: this mode is not supported by the delic-lc. when using collision detection many ghdlcs may start transmitting at the same time. suppose that several ghdlcs start transmitting simultaneously, the first byte transmitted is always a flag which is common to every ghdlc. afterwards each ghdlc transmits it ? s address which is, of course, unique to each ghdlc. when a difference is discovered between the transmitted bit (ltxd) and the collision bit (lcxd), the transmission is aborted. the ghdlc will try to send the message again after it has detected the bus to be idle for a specified time, according to it ? s class. arbitration on a line is such that the ghdlc channel with the lowest address gets the highest priority. all the ghdlc channels are divided up into two groups: classes 8, 9 and classes 10, 11. initially the dsp programs each channel to be either class 8 or 10. if during transmission a bit collision occurs the ghdlc will have to count 8 consecutive ones (in class 8) or 10 consecutive ones (in class 10) before it tries to retransmit. after a certain ghdlc channel succeeds in making a full transmission it ? s class is increased by 1 to 9 or 11 so that if a bit collision occurs the ghdlc channel will have to count more ones before retransmitting. after the ghdlc channel has counted 9 or 11 consecutive ones it ? s class is brought back down to it ? s former level (see itu-t 1.430 section 6.1.4). collision detection in point-to-multi point configuration the ghdlc can perform a bus access procedure and collision detection. as a result, any number of hdlc controllers can be assigned to one physical channel, where they perform statistical multiplexing. when a mismatch between a transmitted bit and the bit on cxd is detected, the ghdlc stops sending further data and an idle is transmitted. as soon as it detects the transmit bus to be idle again, the ghdlc automatically attempts to re-transmit its frame. the dsp programs the hdlc its class and the hdlc performs a priority mechanism to detect idle on the line.
peb 20570 peb 20571 functional description data sheet 122 2001-03-19 preliminary figure 48 point-to-multi point bus structure if a txd and cxd difference occur, the hdlc aborts its transmission, generates an interrupt for the dsp reporting the collision and disables the output of txd (high impedance or ? 1 ? programmable selecting). the hdlc automatically restarts transmission when the bus is detected to be idle again. the hdlc detects idle if cxd was ? high ? for (8 + 2*class + d), where class is a dsp programmable and is 0 for class 1 and 1 for class 2. d is 1 between a success transmission and idle detection on the bus. 4.7.4 ghdlc memory allocation the memory in the ghdlc is build by a 128 x 8 bit ram equally divided between the ghdlc and the dsp. the ghdlc has a receive buffer and a transmit buffer, divided into two blocks. one block is allocated to the ghdlc channel in the receive direction, the other block is read by the dsp. similarly in the transmit buffer, one block is allocated to the ghdlc channel in the transmit direction, the other block is written to by the dsp as shown in figure 49 . note that the ghdlc has higher priority for the buffer access, whereas the dsp is able to read and write the ram at a much higher frequency. the delic contains 4 gdlc controllers. if only one ghdlc controller is used, the visible buffer size is 32 bytes for each direction, for two channels 16 bytes per channel and for 4 channels 8 bytes per channel. memory is allocated to each receive and transmit buffer according to the number of used channels by the following table: dsp hdlc group controller txd cxd rxd txd cxd rxd txd cxd rxd
peb 20570 peb 20571 functional description data sheet 123 2001-03-19 preliminary this leads to the following address configuration: in the receive direction, blocks are swapped in two cases: the receive buffer is full. the swap is issued immediately after the buffer has become full. an end of a frame indication was detected at the beginning of a frame. the frame is programmable to 62.5 s or 10 s ( see chapter 6.2.6.15 ). to avoid a loss of data in case of a buffer full indication followed by an end of frame indication, this condition becomes true only if additionally there was no full interrupt during the previous frame. in the transmit direction blocks are swapped each time a start transmission command is issued in the command register. receive buffer transmit buffer block 0 block 1 block 0 block 1 one channel 32 bytes 32 bytes 32 bytes 32 bytes two channels 16 bytes 16 bytes 16 bytes 16 bytes four channels 8 bytes 8 bytes 8 bytes 8 bytes table 41 ghdlcu receive buffer configuration no. of channels direction channel address ch 0 ch1 ch 2 ch3 1 channel receive 0x2040 transmit 0x2000 2 channels receive 0x2040 0x2060 transmit 0x2000 0x2020 4 channels receive 0x2040 0x2060 0x2070 0x2050 transmit 0x2000 0x2020 0x2030 0x2010
peb 20570 peb 20571 functional description data sheet 124 2001-03-19 preliminary figure 49 ghdlc receive and transmit buffer structure the ghdlc unit and dsp always read and write to different areas in the ram. memory is equally allocated to each of the receive and transmit buffer blocks (32 bytes each). the dsp always writes to the block addresses. the switching between blocks is done internally and does not concern the dsp. 4.7.5 ghdlc interrupts full interrupt: a full interrupt is generated if: the receive buffer is full. the interrupt is issued immediately after the buffer has become full. an end of a frame indication was detected at the beginning of a frame. the frame is programmable to 62.5 s or 10 s ( chapter 6.2.6.15 ). to avoid a loss of data in case of a buffer full indication followed by an end of frame indication, this condition becomes only true if additionally there was no full interrupt during the previous frame. empty interrupt: an empty interrupt is generated every time a transmit buffer was emptied by the ghdlc. note: messages with zero byte data content are not supported. 4.7.6 operational description 4.7.6.1 ghdlc initialization the initialization procedure include writing for each hdlc it ? s configuration to the registers set. the four hdlcs will be arranged according to the specified configuration. ghdlc receive dsp read block block receive buffer ghdlc transmit dsp write block block transmit buffer
peb 20570 peb 20571 functional description data sheet 125 2001-03-19 preliminary 4.7.7 ghdlc protocol features the following ghdlc features related to hdlc protocol may be selected in hdlc mode: collision detection: may be active or inactive (relates only to the transmit direction) flags / ones interframe: flags or ones are transmitted between each frame and are automatically recognized in receive direction. in transmit direction the ghdlcu can be programmed for either interframe. crc mode: two possible settings: 16-bit crc / no crc (relates to both the transmit and receive directions, and only when operating in the hdlc mode). push-pull / open drain: in push pull mode a pin may be driven to ? 1 ? or ? 0 ? . when in open drain mode a pin may be driven to ? 0 ? or high impedance. the ghdlcu is able to receive ? flags ? as well as ? 1 ? as itf. if flags are used as itf the delic is able to detect itf-flags with only one ? zero ? between the ? ones ? (shared ? 0 ? ). figure 50 interframe time fill with shared zero 4.7.8 ghdlc possible data rates for the delic-lc/pb the delic-lc has one ghdlc channel with a data rate of up to 2.048 mbit/s. although the delic-pb features 4 ghdlc channels, not all channels are available for each application. if full duplex operation is assumed and if the receive data comes randomly, it ? s recommended to use not more than two channels with 2 mbit/s or 1 channel with up to 8 mbit/s. the reason for this is that the data flow through the p-interface is limited by the p- access time, the maximum number of interrupts supported by the p and by the dma- access time. assuming a system with 4 x 2 mbit/s ghdlc ports this would mean a worst case interrupt repetition rate of 12.5 s (i.e. 4 x 32 bytes per direction have to be transmitted via a 32 byte mailbox). usually the operating system wouldn ? t allow such a high interrupt rate. however if the performance requirements can be reduced (e.g. not all channels are active at the same time or the hdlc packet size is small or the packet rate is low) then a system with 4 x 2 mbit/s might be reasonable with the delic. data rates other than 2.048, 4.096 and 8.192 mbit/s require an external clock. the delic may be configured to use an external clock for each ghdlc port. end flag end flag start flag itf = flag data itf = flag
peb 20570 peb 20571 functional description data sheet 126 2001-03-19 preliminary 4.7.9 ghdlc using external dma controller one of the four ghdlc channel of the delic-pb can be assigned to the dma mailbox handled by an external dma controller. the detailed handling of dma is described in ? dma mailbox (delic-pb only). ? on page 133 .
peb 20570 peb 20571 functional description data sheet 127 2001-03-19 preliminary 4.8 dsp control unit 4.8.1 general the dsp control unit (dcu) controls the dsp access to delic ? s blocks. it performs the following tasks: dsp program and data address decoding interrupt handling data bus and program bus arbitration dsp run time statistics boot support emulation support 4.8.2 dsp address decoding the dcu decodes the dsp data address bus (dxap) and the dsp program address bus (ppap) for performing the following tasks: generating the dsp memory mapped register controls, based on decoding of the 8 msb lines of the data address bus generating the ghdlc, transiu, hdlcu, iomu and pcmu ram controls generating program and data ram controls upon detection of their address generating the read signal for the program rom 4.8.3 interrupt handling the following events are reported by the various telecom peripheral blocks to the dsp: ghdlc dma mailbox p mailbox iom interface frame synchronization (fsc) interrupt pcm interface frame synchronization (pfs) interrupt the ghdlc, dma mailbox and microprocessor mailbox interrupt sources are assigned to the dsp interrupts (int0, int1 and int2) as shown in figure 42 . the fsc and pfs are reported as status bits (require dsp polling) in the status event register (steve). table 42 interrupt map interrupt source int0 p dma mailbox int1 p general mailbox int2 fsc & pfs nmi ghdlc
peb 20570 peb 20571 functional description data sheet 128 2001-03-19 preliminary note: the nmi interrupt maybe enabled/disabled in the intmask register. 4.8.4 dsp run time statistics the dsp run time statistics is used for the dsp work load estimation. by using this hw, the maximum time spent by the dsp from the fsc until the tasks ends may be found. the dsp statistics include an eight bit counter statc which is counting up every 1 s. figure 51 statistics registers statc is reset upon fsc rising edge. when the dsp finishes a task, it reads statc. the time between two consecutive fsc is always 125 s, therefore, if the dsp is working properly, the counter value should always be less then 125 s. if the dsp failed to read the counter value and a new fsc rising edge has arrived, the counter is not reset. therefore, the dsp reads a value greater then 125. it means that the dsp failed to finish it ? s tasks within the time frame of 125 s. the stati register is added for helping the user to perform the statistics. stati is a general purpose 8-bit read/write register. 1 s dsp reset by fsc of the frame n+1, only if statc the dsp has read the counter already dsp maximum value register counter (in frame n) stati
peb 20570 peb 20571 functional description data sheet 129 2001-03-19 preliminary the user program should perform statistics in the following way: the statc is reset upon detection of fsc rising edge. the dsp finishes its activities and reads the value of statc and stati. the dsp compares statc to the previous maximum value saved in stati. if the new value is larger, it is written to stati. the system programmer = can get the counter value via p mailbox and thus can change the dsp program. 4.8.5 data bus and program bus arbitration the internal data bus (gexdbp) and program data bus (gip) are tri-state buses. since these buses must never float, the dcu keeps track of the bus activities. if during a dedicated cycle no driver is on the bus, the dcu puts a default value on the bus. 4.8.6 boot support the p boot is the process which loads the external p program ram via the p mailbox into the on-chip dsp program ram. the boot is controlled by a boot routine residing in the internal dsp program rom. this routine is started upon delic reset according to the boot strap pin status. the second boot option is the emulation boot, which loads the monitor (bi routine) to the program ram. this routine enables the pc emulator to control the dsp. at system start-up the program code for the dsp is transferred into the internal ram from the external p. the contents for the program and data boot is delivered in a so called hex file. the code format of the hex file is the following: code,:,16 bit address, 16 bit opcode c:0000 4180 c:0001 0018 c:0004 4180 c:0005 00ba c:0006 4180 c:0007 00bd c:000e 4180 c:000f 00be ... the program boot starts with the "start loading program ram" command which is coming from the delic boot routine. ocmd = 0x1f this command must be polled from the p because the interrupt is still not activated. the p confirms this with the "start boot" command. mcmd = 0x55
peb 20570 peb 20571 functional description data sheet 130 2001-03-19 preliminary the program code is now transferred in pieces of maximum 15 words by use of the "write program memory command". mdt0 = 0xdestination_address mdtn = 0xopcode_wordn mcmd = 0xan[n=1..15 number of code words to write to address++] before writing this command, the p must check that the mailbox is free. this is done by reading the mbusy bit (bit 7 of address 0x41). the p must wait until this bit is reset before sending the next command. missing addresses in the hex file must not be loaded. the "write program memory command" must be repeated until the program code is fully loaded. the end of the code segment inside the hex file is the change from c: (code) to d: (data). this is the start of the data segment, which is needed for the data boot, described in the next step. after all the code has been loaded, the "finish boot" command must be sent: mcmd = 0x1f 4.8.7 reset execution and boot strap pin setting the reset is executed via low signals on the delic reset pin (29) and the vip reset pin (44). it is recommended to connect the vip reset inputs to the delic resind output pin (89). the resind signal is a delayed reset signal and stays at least 500 us after termination of the delic reset input. this mechanism ensures that all output clocks of the delic have become stable even after a short reset was applied. connecting the vip reset to this resind signal ensures stable vip clocking after reset (layer1 clock, dcl2000, fsc). together with applying the reset signal to the delic, the strap pin signals must be defined. there are 9 pins at the delic device which have a special functionality. these so called strap pins are used as inputs while reset is active and determine different modes like master/slave mode of the pcm interface, test modes, boot mode,... please refer to page 38 for detailed information about the strap pin options. the settings of the strap signals are sampled with the rising edge of the delic reset input signal. for a p- boot, the default settings of strap 4 (emulation boot) and strap 6 (boot strap) are needed. after a correct reset execution and strap pin setting, the delic sends the command "start loading program ram" to the up: ocmd = 0x1f
peb 20570 peb 20571 functional description data sheet 131 2001-03-19 preliminary 4.9 general mailbox 4.9.1 overview the p and the dsp communicate via a bidirectional mailbox according to the mailbox protocol described in delic-lc/-pb software user ? s manual . the delic provides two dedicated mailboxes that may be used in two operational modes: dma mode in which the two mailboxes operate independently, one serves as a general purpose mailbox and the other serves as a dma mailbox. expanded mailbox mode in which the two mailboxes are regarded as a enlarged general purpose mailbox, providing a double number of registers. the general purpose mailbox includes two separate parts: p mailbox - enables transfers from the p to the oak. oak dsp mailbox - enables transfers from the oak to the p. both parts include a command register, 9 x (16-bit) registers (17 registers in expanded mode) and a busy bit. one of the data registers in every part has a special addressing mode, i.e. the oak may access either a certain byte of a word or the whole word which is temporarily stored in the mailbox. this requires to use 3 different addresses in oak ? s direction. note: the mailbox protocol commands structure is described in delic-lc/-pb software user ? s manual . 4.9.2 p mailbox the p mailbox includes: eight 16-bit data registers (mdtn) a16-bit general register (mgen) an 8-bit command register (mcmd) a 1-bit busy register (mbusy) registers mdtn, mgen and mcmd may be written by the p and read by the oak. the mbusy register may be written by the dsp and read by the p. a write of the p to the mcmd-register of the p-mailbox generates an interrupt to the oak. thus, the user has to provide all mailbox data prior to writing to register mcmd. the mbusy bit which may be read by the p (register mbusy) is set automatically after a write to the p command register (mcmd) and reset automatically by a direct oak write operation to it. note: the command opcodes are defined in delic-lc/-pb software user ? s manual .
peb 20570 peb 20571 functional description data sheet 132 2001-03-19 preliminary data transfer from the p to the oak the p reads the busy bit and checks whether the mailbox is available (mbusy= ? 0 ? ) the p writes to the data registers mdtn (optional) the p writes to the p command register (mcmd), this write must be performed and sets automatically the p mailbox busy bit (mbusy). an oak interrupt (int2) is activated due to the write to the command register (mcmd). the oak int2 routine reads mcmd and performs the command (the read of the command register resets the int2 activation signal). when finished, the int2 routine resets mbusy for enabling the p to send the next command. note: the p may perform consecutive writes to the p mailbox, and the user must guarantee that the data has been transferred to the oak correctly (the busy bit has been reset) before writing new data to the p mailbox. 4.9.3 oak mailbox the oak mailbox includes: eight 16-bit data registers (odtx) a 16-bit general register (ogen) an 8-bit command register (ocmd) a 1-bit busy register (obusy) registers odtx, ogen and ocmd may be written by the oak and read by the p. the obusy bit may be written by the p and read by the oak. in addition, the p can read this bit (because the p could poll this bit). a write of the oak to register ocmd of the oak mailbox generates an interrupt to the p. thus the oak firmware provides all mailbox data prior to writing to register ocmd. the obusy- bit which can be read by the oak, is set automatically after a write of the oak to register ocmd and is reset by a direct p write to it (when the p has finished reading the oak mailbox contents). note: the opcodes indications are defined in delic-lc/-pb software user ? s manual .
peb 20570 peb 20571 functional description data sheet 133 2001-03-19 preliminary data transfer from the oak to the p the oak reads the busy bit and checks whether the mb is available (obusy= ? 0 ? ) the oak writes to the data registers odtn (optional) the oak writes to the command register (ocmd). this write must be performed and automatically sets the oak mailbox busy bit (obusy) a p interrupt is activated due to the write operation to the register ocmd. the p reads the command register and performs the command. when finished, the p resets obusy for enabling the oak to send the next command. note: the oak may perform consecutive writes to the oak mailbox and the oak firmware guarantees that the data has been transferred to the p correctly (obusy reset) before writing new data to the oak mailbox. 4.10 dma mailbox (delic-pb only). the delic provides two dedicated mailboxes that may be used in two different ways: 1. in dma mode, one may be used as a dma mailbox ( 16 bytes) and one as general purpose mailbox ( 16 bytes) . both mailboxes operate independently. 2. in expanded mailbox mode, the two mailboxes are regarded as one large general purpose mailbox, providing double number of registers ( 32 bytes) . the mailbox mode can be configured in the configuration register (mcfg:dma). the 16-byte deep dma mailbox connects the delic and an external dma controller. the dma mailbox can be accessed only by the dma controller and only upon a request from delic. note: the p can not access the dma mailbox. it can access directly only the general mailbox. the dma mailbox can be used for different data transfers, e.g.: data transfer via ghdlc (e.g. 2 mbit/s) transfer of d-channel signaling data (16 kbit/s) recording and replay of voice channels (64 kbit/s) fast data transfers between external and delic internal memories the dma mailbox consists of two separate parts: transmit mailbox - for dma data transfer from memory to delic. receive mailbox - for dma data transfer from delic to memory. in order to transmit data, the delic must initiate a dma request for transmit data (dreqt); for receiving data, it initiates dreqr. the dma controller answers with dma acknowledge (dack) signal together with rd or wr signal (intel/infineon bus type), or r/w and ds (motorola bus type). which signals are used depends on the selected
peb 20570 peb 20571 functional description data sheet 134 2001-03-19 preliminary dma mode, and the data transfer direction. two dma modes are supported: two-cycle dma transfer mode called also memory-to-memory mode single cycle dma transfer mode called also fly-by mode an example for a two-cycle dma transfer in receive direction (data is read from delic and written to memory) in intel/infineon mode is shown in figure 52 . figure 52 two-cycle dma transfer mode for receive direction 1. the dma mailbox contains data (the receive mailbox contains up to 16 bytes of data) 2. delic requests dma service via dreqr 3. dma controller issuses a dma acknowledge (dack) signal for addressing the dma mailbox and a "read" signal for indicating delic that it will read the receive mailbox 4. the dma controller reads the data into an on-chip register (= end of first cycle). 5. the dma controller writes the data into the memory using addr and wr (= second cycle). the main advantage of the two-cycle dma transfer mode, compared to general mailbox access by a p, is its faster response time (depends on the operating system) and a simple data flow control. memory data bus dma controller delic data dack + rd dma mailbox memory data bus dma controller delic data 2-cycle-mode addr wr dreqr 1. cycle 2. cycle dma mailbox
peb 20570 peb 20571 functional description data sheet 135 2001-03-19 preliminary figure 53 single cycle dma transfer mode for receive data example for a single-cycle dma transfer mode in receive direction (data is read from delic and written to memory) in intel/infineon mode. figure 53 : 1. the dma mailbox contains data (the receive mailbox contains up to 16 bytes of data) 2. delic requests dma service via dreqr 3. dma controller issuses a dma acknowledge (dack) signal for addressing the dma mailbox and a "read" signal for indicating delic that it will read the receive mailbox 4. in parallel, when the read data are stable on the bus, the dma controller writes the data directly into the memory using addr and wr. note: in intel/infineon mode, wr is used as "read" signal for the receive mailbox. an example for a single-cycle dma transfer in intel/infineon mode in transmit direction (data is read from memory and written into delic) is shown in figure 54 : memory 1-cycle-mode data bus dma controller delic dma mailbox data addr dreqr wr dack + wr
peb 20570 peb 20571 functional description data sheet 136 2001-03-19 preliminary figure 54 single cycle dma transfer mode for transmit data 1. the dma transmit mailbox is empty 2. delic requests dma service via dreqt 3. the dma controller addresses memory with addr and the delic with dack 4. with read signal (rd), memory data reach the data bus 5. in parallel, when the data are stable on the bus, the dma controller writes it directly into the transmit mailbox. note: in intel/infineon mode, rd is used as write signal for the transmit mailbox. 4.10.1 dma handshake in transactions between dma controller and delic, the delic indicates that it is ready to transmit/ receive data by setting dreqt / dreqr high. the dma controller answers by driving dack low. dack acts like a cs and remains low during the entire transaction. by driving dack high, the dma controller can stop the transaction on any stage, even if the data transfer has not been finished yet. delic programming 1. set the dma transfer mode in mcfg register by the p to memory-to-memory or fly- by mode. memory 1-cycle-mode-t data bus dma controller delic dma mailbox data addr dreqt rd dack + rd
peb 20570 peb 20571 functional description data sheet 137 2001-03-19 preliminary 2. select the type of used data bus via delic pin "mode": intel/ infineon or motorola 3. set byte count by writing the number of bytes to be transferred, minus 1, into dtxcnt/drxcnt register (is handled by the oak firmware). 4. et the end of a transaction, oak int0 is automatically activated (if not masked) in order to indicate that the mailbox is empty and available for a next operation. the oak can mask int0 as a whole or just one of its components (for receive or transmit direction) via register dinsta. 4.10.1.1 two-cycle dma transfer mode depending on the selected bus mode (intel / infineon or motorola), different signals are used. in intel/infineon mode, the control lines are dack , rd , wr . driving rd low when dack is low causes a read from the mailbox. driving wr low when dack is low causes a write into the mailbox. in motorola mode, the control lines are dack , r/w , ds . driving r/w high when dack and ds are low causes a read from the mailbox. driving r/w low when dack and ds are low causes a write into the mailbox. 4.10.1.2 fly-by mode in fly-by mode, the dma transfer is done in one bus transaction. the dma controller controls the dma mailbox and the conventional memory within the same cycle; write strobe just when the read data is valid on the bus. see timing diagrams for intel/infineon and for motorola bus type in chapter 8 . 4.10.2 pec mode. the pec-mode supports infineon ps c16x, which use an integrated peripherals event controller (pec) as a dma controller. this dma controller is edge sensitive, meaning edges have to be provided on the dreq line in order to initiate every dma transfer. dreq is internally controlled by the read/write signals. wr falling edge disables dreqt, i.e. drives it inactive, and rd falling edge does the same for dreqt. rising edges of these signals enable dreqs again. 4.10.3 transmit = dma = mailbox the transmit dma mailbox includes: a 16-byte fifo which the dma controller writes in (addresses tdt0-7) and the oak reads out as from 8 regular 16-bit-wide registers. a 4-bit counter for indicating the number of transfers remaining in the current transaction (register dtxcnt).
peb 20570 peb 20571 functional description data sheet 138 2001-03-19 preliminary a 4-bit interrupt status register (dinsta), which actually belongs to both directions - transmit and receive. the delic initiates all transfers, i.e. each transmit is initiated by the oak. but the transfers are carried out by the dma controller. if the delic transmits data e.g. to the ghdlc unit, the oak writes the requested number of bytes (minus 1) into the dtxcnt register which causes the assertion of dreqt ( ? dma request for transmit direction ? ) pin. the dma controller grants the bus to the delic, it drives dack low and begins toggling the control lines. in intel / infineon (memory-to-memory) mode it drives wr line low when writing a byte to the mailbox. rd line stays high during all the ? write ? transfer. dack functions as a cs and is driven low during each ? write ? access. refer to ac specification, in chapter 8 . figure 55 timing in two-cycle dma mode for transmit direction and infineon/ intel bus type in motorola (memory-to-memory) mode the dma controller drives r/w line low during ? write ? operations when dack is low and ds is used for access timing. in fly-by mode the meaning of ? read ? and ? write ? commands is opposite for the mailbox ( see chapter 4.10.1.2 ). after every ? write ? operation the counter (dtxcnt) is decremented by one. dma-operation is finished with the count down from 0 h to the value ? f h ? . the dma controller can stop the transaction (before frame end) driving d ack high. the delic continues keeps dreqt active, stops decrementing dtxcnt and waits until dack becomes low again. dsp-tasks wr dtxcnt dreqt wr dack oak - int0 16 12 isr: wr dtxcnt
peb 20570 peb 20571 functional description data sheet 139 2001-03-19 preliminary after the dma controller has written the requested number of bytes to the transmit mailbox, dtxcnt becomes ? f h ? , and dreqt is deasserted. register dinsta can be programmed to cause an interrupt (int0) to the oak. the oak can now read the data from the transmit mailbox: - 1st byte in least significant (ls) byte of ls word of the fifo - 2nd byte in most significant (ms) byte of ls word of the fifo, and so on note: 1. in case of an odd number of bytes, the last byte is available as the ls byte of the last word while the ms byte of this word is do not care. 2. the oak reads data word-by-word, exactly like in a non-dma transfer. data transfer via the transmit mailbox - steps 1. the oak writes into dtxcnt the number of bytes to be transferred minus one (tr_num). 2. dreqt is asserted ( ? high ? or ? low ? depending on register mcfg:drqlv). 3. the dma asserts dack = 0 and issues (tr_num+1) write transactions to the mailbox ( ? fifo ? ). 4. dreqt is deasserted ( ? low ? or ? high ? ). 5. if bit dinsta:tmsk is inactive ( ? 1 ? ), the dma interrupt (int0) of the oak is activated. 6. the oak reads tr_num bytes from the mailbox. note: the oak must not write to the register dtxcnt while the previous dma transfer has not been finished. (the oak waits for transmit dma interrupt and tests if dtxcnt equals ? f h ? .) 4.10.4 receive dma mailbox the receive mailbox includes: a 16-byte fifo which the oak writes into as in 8 regular 16-bit-wide registers and the dma controller reads out like from a fifo (rdt0-7). a 4-bit counter for indicating the number of transactions that remain for the transfer (drxcnt). the delic initiates all transfers, i.e. each receive is initiated by the oak. but the transfers are done by the dma controller. when the delic receives data e.g. from the ghdlc unit, the oak writes this data into the receive mailbox whereas the 1st byte is put into ls byte of ls word, the 2nd byte into ms byte of ls word, and so on. note: in case of an odd number of bytes, the ms byte of the last word is don ? t care. then the oak writes the byte count into register drxcnt, which causes the assertion of dreqr ( ? dma request for receive direction ? ) pin.
peb 20570 peb 20571 functional description data sheet 140 2001-03-19 preliminary if the dma controller grants the bus to the delic, it drives dack low and begins toggling the control lines. in memory-to-memory mode on intel / infineon bus type, it drives rd line low when reading from the receive mailbox. the wr line stays high during all the ? read ? transfer. dack functions as a cs and is driven low during each ? read ? access. in memory-to-memory mode on motorola bus type, the dmac drives r/w line ? high ? during ? read ? operations while dack is low and ds controls the read access. in fly-by mode the meaning of ? read ? and ? write ? commands is opposite for the mailbox ( see chapter 4.10.1.2 ). after each ? read ? operation the counter (drxcnt) is decremented by one. dma-operation finishes with the count down from 0 h to the value ? f h ? . the dma controller can stop the transaction (before frame end) driving dack high. the delic continues driving dreqr active, stops decrementing drxcnt and waits until dack becomes low again. after the dma controller has read the requested number of bytes from the receive mailbox, drxcnt becomes ? f h ? , and dreqr is deasserted. dinsta can be programmed to cause an interrupt (int0) to the oak. figure 56 timing in two-cycle dma mode for receive direction and infineon/ intel bus type receive data via the receive mailbox-steps 1. the oak writes the received data to into the receive mailbox. 2. the oak writes the number of bytes to be transferred minus one into drxcnt (rc_num). 3. dreqr is asserted ( ? high ? or ? low ? ). dsp-tasks wr drxcnt dreqr rd dack oak - int0 16 12 isr int0: wr drxcnt
peb 20570 peb 20571 functional description data sheet 141 2001-03-19 preliminary 4. the dma controller asserts dack and issues (rc_num+1) read transactions from the receive mailbox ( ? fifo ? ). 5. dreqr is deasserted ( ? high ? or ? low ? ). 6. if rmsk bit in dinsta is inactive ( ? 1 ? ), the dma interrupt to oak (int0) is activated. note: the oak must not write to the register drxcnt while the previous dma receive transaction has not been finished. (the oak waits for receive dma interrupt and tests if dtxcnt equals ? f h ? .) 4.10.5 fifo access the fifo size is 16 bytes (8 words) each (transmit, receive). on the oak side, each of the 8 data registers (tdt0-7 and rdt0-7) can be accessed separately. on the dma controller side, only the current top of fifo is accessible. note: the transmit fifo and the receive fifo are functioning as explained above only when the mailbox is in dma mode (mcfg:dma = ? 1 ? ). in case of non-dma mode (mcfg:dma = ? 0 ? ) the fifos are used as secondary (extension) to the general mailbox, which means that the general mailbox will have 16 words for each direction (oak and p ), instead of 8.
peb 20570 peb 20571 functional description data sheet 142 2001-03-19 preliminary 4.11 clock generator 4.11.1 overview the delic clock generator provides all necessary clock signals for the delic and connected clock slave devices. the internal clocks are generated by two on-chip plls: 1. a digital controlled oscillator (dcxo) generates a 16.384 mhz clock from an external crystal. 2. a pll multiplies the 16.384 mhz clock to a 61.44 mhz clock. an overview of the clock signals and a block diagram is shown below. table 43 overview of clock signals pin function i/o during reset clk16-xi 16.384 mhz external crystal input i i clk16-xo 16.384 mhz external crystal output o o xclk external reference clock from layer-1 ic (2.048 mhz, 1.536 mhz or 8 khz) ii (1.536 mhz) refclk pcm reference clock (8 khz or 512 khz) i/o tristate pfs pcm frame synchronization 8 khz (i/o) or 4 khz (i) i/o i (slave) o (master) pdc pcm data clock (2.048, 4.096, 8.192 or 16.384 mhz) i/o i (slave) o (master) (2.048 mhz) clkout auxiliary clock (2.048, 4.096, 8.192, 16.384, or 15.36 mhz) oo (4.096 mhz) dcl_2000 iom-2000 data clock (3.072, 6.144 or 12.288 mhz) o o (3.072 mhz) dcl iom-2 data clock (384 khz, 768 khz, 2.048 mhz or 4.096 mhz) oo (384 khz) fsc iom-2 and iom-2000 frame synchronization 8 khz. o o l1_clk layer-1 clock 15.36 or 7.68 mhz (e.g. octat-p / quat-s) oo (7.68 mhz) dsp_clk dsp test clock. (to run the dsp at clock rates other than 61.44 mhz) ii
peb 20570 peb 20571 functional description data sheet 143 2001-03-19 preliminary figure 57 delic clock generator 61.44 :2 15.36 mhz :8 mux dsp clk 8 khz delic pd pll 16.384 mhz mux 6.144 mhz dcl_2000 12.288 mhz :20 pdc dcl pfs m/s 3.072 mhz :2 7.68 mhz :1 dcxo clk16-xi clk16-xo filter 16.384 mhz :2 m/s(strap :64 :1 512 khz / 8 khz refclk shp short fsc (fallback) dsp_clk (reference clock :2 :15 :30 :2 :256 :512 fsc 8 khz clkout 2.048 mhz 4.096 mhz :2 :2 :256 8.192 16.384 mhz mhz 4.096 mhz 2.048 mhz 8 khz 2.048 mhz 4.096 mhz 8.192 mhz 16.384 mhz mux xclk (reference clock from l1 device, 1.536 mhz or 2.048 mhz or 8 khz) pcm) :192 :256 :1 8 khz 8 khz refs :3 :4 :192 :256 8 khz :10 :5 mhz :1 :2 l1_clk :80 :160 384 khz 768 khz :48 :96 lclk mux ghdlc 1.536 mhz 15.36 mhz option)
peb 20570 peb 20571 functional description data sheet 144 2001-03-19 preliminary 4.11.2 dsp clock selection the default dsp clock is the internal 61.44 mhz generated by the pll. for test purpose, a different frequency may be provided via dsp_clk input pin. the selection between the internal 61.44 mhz or external clock source is done by the dsp_frq input pin. 4.11.3 pcm master/slave mode clocks selection in pcm master mode, the pfs and pdc are derived from the internal 16.384 mhz signal, and driven to the pcm interface via the pfs pin (output) and pdc pin (output). in pcm slave mode, the pfs and pdc are generated from an external signal, and input to the delic via the pfs pin and the pdc pin. note: during reset, a strap pin determines whether the delic operates in clock master or slave mode. when setting to slave mode the register pfs sync ( chapter 6.2.11.10 ) has to be written in order to align the clocks. 4.11.4 delic clock system synchronization the pcm clock division chain is synchronized to an external reference clock, used as one of the inputs to a phase comparator, after being divided into 8 khz. the other phase comparator input is the 8 khz clock, derived from the 16.384 mhz clock. the phase comparator output is used as control input of the dcxo, after being filtered by a low-pass filter. the reference clock can be driven by one of the following input pins: xclk - 2.048 mhz, 1.536 mhz or 8 khz: can be driven by a layer-1 transceiver (e.g. vip, quat-s) connected to the central office. only a clock master delic can be synchronized directly according to this input. in other cases (clock slave delic), this input signal may be divided to 8 khz or 512 khz, and driven out via refclk, in purpose to be used for the synchronization of the clock-master delic. refclk - 512 khz or 8 khz: used for synchronization of the clock master delic, when not synchronized by xclk. usually this signal is driven by a clock slave delic, or another pbx in the system. in a clock slave delic this pin is used as output. pfs - 8 khz: driven by the system clock master. may be used for synchronization of the clock slave delics. in a clock master delic this pin is used as output. 4.11.5 iom-2 clock selection the iom-2 interface clocks fsc and dcl are always output. the fsc output signal is usually generated with 50% duty cycle. a short fsc pulse is required for multiframe start indication (one dcl cycle long). one cycle after the short fsc pulse, the normal fsc is generated again with 50% duty cycle.
peb 20570 peb 20571 functional description data sheet 145 2001-03-19 preliminary 4.11.6 iom-2000 clock selection the iom-2000 interface uses the same fsc like iom-2, whereas the data clock dcl2000 is a dedicated pin (always output). 4.11.7 refclk configuration refclk is an i/o pin for synchronizing the pcm interface (to 8 khz or 512 khz). the clock master delic may synchronize the internal clocks to refclk by selecting refclk as the reference clock source. a clock slave delic may use refclk as output, when refclk is driven by the xclk input pin. the slave delic may transfer the xclk signal to the clock master delic, and enable the clock master to synchronize to a layer-1 device, which is connected to another delic in the system. 4.11.8 ghdlc clock selection any of the next signals may be provided to the ghdlc channel as input clock: 1. lclk input pin this option is possible only when a lnc interface is assigned to the ghdlc unit. 2. 2.048 mhz, 4.096 mhz, 8.192 mhz or 16.384 mhz these clock signals are generated internally by the pcm clocking path. the selected internal clock is also driven outward via lclk. note: one of these signals must be selected as the clock of the ghdlc channel when the delic is the clock master of this channel. note: it ? s not possible to operate a ghdlc-channel with 16.384 mhz. however if the respective port isn ? t used this clock can be driven externally.
peb 20570 peb 20571 delic memory structure data sheet 146 2001-03-19 preliminary 5 delic memory structure the following tables provide the delic memory map for the dsp and the p. 5.1 dsp address space 5.1.1 dsp register address space t 5.1.2 dsp program address space table 44 dsp registers address space address description d000 - d01f dcu registers d020 - d03f a/-law registers d040 - d05f iomu registers d060 - d07f pcmu registers d080 - d09f clocks registers d0a0 - d0bf transiu registers d0c0 - d0df ghdlc registers d100 - d17f p mailbox and dma mailbox registers d180 - d1ff hdlcu registers d1a0 - dfff not used table 45 dsp program address space address size description 0000 - 0fff 4kw program ram 1000 - f7ff 58kw not used f800 - ffff 2kw program rom
peb 20570 peb 20571 delic memory structure data sheet 147 2001-03-19 preliminary 5.1.3 dsp data address space a1 table 46 occupied dsp data address space address size description 0000 - 03ff 1kw internal xram 2000 - 203f 64w ghdlc data buffer 2040 - 207f 64w reserved for test (**) 4000 - 401f 32w hdlcu receive output buffer 4020 - 403f 32w hdlcu transmit input buffer 4040 - 405f 32w hdlcu command ram 4060 - 407f 32w hdlcu receive input buffer 4080 - 409f 32w hdlcu transmit output buffer 40a0 - 40bf 32w hdlcu status buffer 6000 - 605f 96w transiu receive data buffer 6080 - 60df 96w transiu transmit data buffer 6100 - 61bf 192w reserved for test (**) 6200 - 6248 72w reserved for test (**) 6280 - 62c8 72w reserved for test (**) 8000 - 803f 64w iomu receive data buffer 8040 - 807f 64w iomu transmit data buffer 8080 - 80ff 128w reserved for test (**) 9000 - 9017 24w hram for u pn scrambler 9020 - 9037 24w hram for u pn descrambler a000 - a07f 128w pcmu receive data buffer a080 - a0ff 128w pcmu transmit data buffer a100 - a1ff 256w reserved for test (**) d000 - dfff 4kw oak memory mapped registers(*) e000 - e1ff 0.5kw a/ -law rom f400 - f7ee 1kw-16w emulation mail box (on scdi) f7f0 - f7ff 16w ocem registers fc00 - ffff 1kw internal yram
peb 20570 peb 20571 delic memory structure data sheet 148 2001-03-19 preliminary note: (*) the oak memory mapped registers address space is described in the following table: (**) accessing these addresses may cause unpredictable results. for connecting a hdlc channel to a subscriber, the receive and transmit time slot address must be determined. usually the hdlc channels perform signalling to a terminal which can be accessed via iom2 or iom2000 interface. either d-channel handling (2 bit) or signalling via a b-channel (8 bit) can be selected. the following figures show the memory organization and help to determine initialization addresses for the hdlc software registers. the transiu receive and transmit buffers are accessed directly by the dsp: switching- and hdlc-tasks. accesses to the ? operation mode command and status bits ? are possible via addresses: 6003 h + n * 4 with n = 0..23. table 47 oak memory mapped registers address space address description d000 - d01f dcu registers d020 - d03f a/m-law registers d040 - d05f iomu registers d060 - d07f pcmu registers d080 - d09f clocks registers d0a0 - d0bf transiu registers d0c0 - d0df hdlcu registers d100 - d17f cpu+dma mailbox registers d180 - d1ff ghdlc registers d1a0 - dfff not used
peb 20570 peb 20571 delic memory structure data sheet 149 2001-03-19 preliminary figure 58 transiu buffer addresses 6000 h ... transiu receive buffer b1-channel data b2-channel data d 6001 h 6002 h 6003 h b1-channel data b2-channel data d 6004 h 6005 h 6006 h 6007 h 605c h b1-channel data b2-channel data d 605d h 605e h 605f h 6080 h ... b1-channel data b2-channel data d 6081 h 6082 h 6083 h b1-channel data b2-channel data d 6084 h 6085 h 6086 h 6087 h 60dc h b1-channel data b2-channel data d 60dd h 60de h 60df h vip0 channel 0 vip0 channel 1 vip2 channel 7 vip0 channel 0 vip0 channel 1 vip2 channel 7 transiu transmit buffer
peb 20570 peb 20571 delic memory structure data sheet 150 2001-03-19 preliminary 5.2 p address space the p address space consists of the general mail-box registers, the dma mail-box registers (only in non-dma mode), the p-interface control register, and the p-interface status register (misr) . table 48 p address space table address description 00 h - 43 h 60 h - 62 h p- mail box registers 48 h , 68 h , 6a h p-configuration registers 6b h - 7f h reserved. accessing these addresses may cause unpredictable results
peb 20570 peb 20571 register description data sheet 151 2001-03-19 preliminary 6 register description 6.1 register map table 49 transiu register map reg name access address reset value comment page no. ticr rd/wr d0a0 h 0000 h iom-2000 global configuration 161 tccr0 rd/wr d0a1 h ffff h channel 7..0 configuration 162 tccr1 rd/wr d0a2 h ffff h channel 15..8 configuration 162 tccr2 rd/wr d0a3 h ffff h channel 23..16 configuration 162 vipcmr0 wr d0a8 h 0000 h vip_0 command registers 164 vipcmr1 wr d0a9 h 0000 h vip_1 command registers 164 vipcmr2 wr d0aa h 0000 h vip_2 command registers 164 vipstr0 rd d0ac 0000 h vip_0 status register 167 vipstr1 rd d0ad h 0000 h vip_1 status register 167 vipstr2 rd d0ae h 0000 h vip_2 status register 167 ticcmr wr d0b0 h (ls-word) d0b1 h (ms-word) 0000 h 0000 h channel initialization command 168 ticstr rd d0b2 h (ls-word) d0b3 h (ms-word) 0000 h 0000 h channel initialization status 173 tutlr rd/wr d0b4 h (ls-word) d0b5 h (ms-word) 0000 h 0000 h up test loop register 174
peb 20570 peb 20571 register description data sheet 152 2001-03-19 preliminary table 50 scrambler register map reg name access address reset value comment page no. scmod rd/wr d010 h 0003 h scrambler mode 175 scsta rd/wr d011 h undef. scrambler status 176 table 51 iomu register map reg name access address reset value comment page no. icr r/w d040 h 0002 h iomu control 177 isr r d041 h undef. iomu status 178 itscr set (w) d042 h 0000 h iomu tri-state control 179 reset (w) d043 h r d044 h idrdyr r d045 h undef. iomu drdy 181 idpr r/w d046 h 00e0 h iomu data prefix 182 table 52 pcmu register map reg name access address reset value comment page no. pcr rd/wr d060 h 00 h pcmu control 183 psr rd d061 h undef. pcmu status 184 ptsc0 rd/wr d062 h (read/set) d063 h (read/reset) 00 h pcmu tristate control 0 185 ptsc1 rd/wr d064 h (read/set) d065 h (read/reset) 00 h pcmu tristate control 1 185 ptsc2 rd/wr d066 h (read/set) d067 h (read/reset) 00 h pcmu tristate control 2 185
peb 20570 peb 20571 register description data sheet 153 2001-03-19 preliminary . ptsc3 rd/wr d068 h (read/set) d069 h (read/reset) 00 h pcmu tristate control 3 185 ptsc4 rd/wr d06a h (read/set) d06b h (read/reset) 00 h pcmu tristate control 4 185 ptsc5 rd/wr d06c h (read/set) d06d h (read/reset) 00 h pcmu tristate control 5 185 ptsc6 rd/wr d06e h (read/set) d06f h (read/reset) 00 h pcmu tristate control 6 185 ptsc7 rd/wr d070 h (read/set) d071 h (read/reset) 00 h pcmu tristate control 7 185 pdpr rd/wr d072 h e0 h pcmu data prefix 187 table 53 a-/-law unit register map reg name access address reset value comment page no. amcr r/w d020 h 00 h a/-law unit control 188 amir w d021 h undefin ed a/-law unit input 189 amor r d022 h undefin ed a/-law output 190 table 52 pcmu register map (cont ? d) reg name access address reset value comment page no.
peb 20570 peb 20571 register description data sheet 154 2001-03-19 preliminary table 54 hdlcu register map reg name access address reset value comment page no. hcr w d180 h 0001 h hdlc control 191 hsta r d180 h 0001 h hdlc status 192 hccv r/w 4040 h -405f h undefin ed channel command vector 193 hcsv r 40a0 h -40bf h undefin ed channel status vector 195 table 55 ghdlc register map reg name access address reset value comment page no. gtest w d0c0 h 0001 h ghdlc test/ normal mode 197 gchm w d0c1 h 0000 h ghdlc channel mode 198 gint r d0d4 h 0000 h ghdlc interrupt 199 gfint r/w d0d3 h 0000 h ghdlc frame interrupt 200 grsta0 r d0c2 h 001f h ghdlc receive status cha. 0 201 grsta1 r d0c3 h 001f h ghdlc receive status cha. 1 201 grsta2 r d0c4 h 001f h ghdlc receive status cha. 2 201 grsta3 r d0c5 h 001f h ghdlc receive status cha. 3 201 rxdat rd 2000 h - 203f h 0000 h receive data and status 203 gmod0 w d0c6 h 0140 h ghdlc mode cha. 0 204 gmod1 w d0c7 h 0140 h ghdlc mode cha. 1 204 gmod2 w d0c8 h 0140 h ghdlc mode cha. 2 204 gmod3 w d0c9 h 0140 h ghdlc mode cha. 3 204 gtcmd0 w d0ca h 0000 h ghdlc tx command cha. 0 206 gtcmd1 w d0cc h 0000 h ghdlc tx command cha. 1 206 gtcmd2 w d0ce h 0000 h ghdlc tx command cha. 2 206 gtcmd3 w d0d0 h 0000 h ghdlc tx command cha. 3 206 gasync r/w d0d2 h 0000 h async control/ status 207 glclk0 r/w d08a h 0000 h lclk0 control register 208
peb 20570 peb 20571 register description data sheet 155 2001-03-19 preliminary glclk1 r/w d08b h 0000 h lclk1 control register 209 glclk2 r/w d08c h 0000 h lclk2 control register 210 glclk3 r/w d08d h 0000 h lclk3 control register 211 muxctrl r/w d14a h 0000 h multiplexer control 212 st2 w oak register xxxx xx0x xxxx xxxx b ghdlcu frame frequency 213 table 56 dcu register map reg name access address reset value comment page no. imask r/w d002 h 0000 h interrupt mask 214 steve r d003 h 0000 h status event 215 statc r d004 h unchan. statistics counter 216 stati r d005 h 0000 h statistics 217 table 57 p configuration register map reg. (16 bit) des- cription reset value bit dsp word access p byte access p- addr. msb of word p- addr. lsb of word dsp addr. page no. mcfg configur ation 0 h 6 r r/w none 48 h d148 h 218 ivec int vector reg un- changed 8 r/w r none 68 h d168 h 220 table 55 ghdlc register map (cont ? d) reg name access address reset value comment page no.
peb 20570 peb 20571 register description data sheet 156 2001-03-19 preliminary table 58 general mailbox register map reg- ister (16 bit) descrip- tion reset value bit dsp word access p byte acc. p- addr. msb of word p- addr. lsb of word dsp addr. pag e no. mcmd p command 00 h 8 r w none 40 h d140 h 221 mbus y p mb busy 0 h 1w r 41 h none d141 h 222 mgen p generic data reg. unchanged 16 r w 43 h 42 h d142 h (lsb) d143 h (msb) d144 h (all) 223 mdt0 p data reg0 unchanged 16 r w 01 h 00 h d100 h 224 mdt1 p data reg1 unchanged 16 r w 03 h 02 h d102 h 224 mdt2 p data reg2 unchanged 16 r w 05 h 04 h d104 h 224 mdt3 p data reg3 unchanged 16 r w 07 h 06 h d106 h 224 mdt4 p data reg4 unchanged 16 r w 09 h 08 h d108 h 224 mdt5 p data reg5 unchanged 16 r w 0b h 0a h d10a h 224 mdt6 p data reg6 unchanged 16 r w 0d h 0c h d10c h 224 mdt7 p data reg7 unchanged 16 r w 0f h 0e h d10e h 224 ocmd dsp command 00 h 8 w r none 60 h d160 h 225 obus y dsp mb busy 0 h 1r r/w61 h none d161 h 226
peb 20570 peb 20571 register description data sheet 157 2001-03-19 preliminary note: mdt8..15 and odt8..15 are accessible only in non-dma mode, when the dma mailbox data registers are used for doubling the size of general mailbox. ogen dsp generic data reg unchanged 16 w r 63 h 62 h d162 h (lsb) d163 h (msb) d164 h (all) 227 odt0 dsp data reg0 unchanged 16 w r 21 h 20 h d120 h 228 odt1 dsp data reg1 unchanged 16 w r 23 h 22 h d122 h 228 odt2 dsp data reg2 unchanged 16 w r 25 h 24 h d124 h 228 odt3 dsp data reg3 unchanged 16 w r 27 h 26 h d126 h 228 odt4 dsp data reg4 unchanged 16 w r 29 h 28 h d128 h 228 odt5 dsp data reg5 unchanged 16 w r 2b h 2a h d12a h 228 odt6 dsp data reg6 unchanged 16 w r 2d h 2c h d12c h 228 odt7 dsp data reg7 unchanged 16 w r 2f h 2e h d12e h 228 table 58 general mailbox register map (cont ? d) reg- ister (16 bit) descrip- tion reset value bit dsp word access p byte acc. p- addr. msb of word p- addr. lsb of word dsp addr. pag e no.
peb 20570 peb 20571 register description data sheet 158 2001-03-19 preliminary table 59 dma mailbox register map register description reset value bit dsp acces s dma / p acc. p msb addr. p lsb addr. dsp addr. page no. dtxcn t tx counter 0 h 4 r/w none none none d150 h 229 dinsta dma int status 0 h 4 r none none none d152 h 231 tdt0/ mdt8 tx data reg0/ p data reg8 un- change d 16 r w 11 h 10 h d110 h 224 tdt1/ mdt9 tx data reg1/ p data reg9 un- change d 16 r w 13 h 12 h d112 h 224 tdt2/ mdt10 tx data reg2/ p data reg10 un- change d 16 r w 15 h 14 h d114 h 224 tdt3/ mdt11 tx data reg3/ p data reg11 un- change d 16 r w 17 h 16 h d116 h 224 tdt4/ mdt12 tx data reg4/ p data reg12 un- change d 16 r w 19 h 18 h d118 h 224 tdt5/ mdt13 tx data reg5/ p data reg13 un- change d 16 r w 1b h 1a h d11a h 224 tdt6/ mdt14 tx data reg6/ p data reg14 un- change d 16 r w 1d h 1c h d11c h 224 tdt7/ mdt15 tx data reg7/ p data reg15 un- change d 16 r w 1f h 1e h d11e h 224 drxcn t rx counter 0 h 4 r/w none none none d170 h 230 rdt0/ odt8 rx data reg0/ dsp data reg8 un- change d 16 w r 31 h 30 h d130 h 228
peb 20570 peb 20571 register description data sheet 159 2001-03-19 preliminary note: mdt8..15 and odt8..15 are accessible only in non-dma mode, when the dma mailbox data registers are used for doubling the size of general mailbox. .. rdt1/ odt9 rx data reg1/ dsp data reg9 un- change d 16 w r 33 h 32 h d132 h 228 rdt2/ odt10 rx data reg2/ dsp data reg10 un- change d 16 w r 35 h 34 h d134 h 228 rdt3/ odt11 rx data reg3/ dsp data reg11 un- change d 16 w r 37 h 36 h d136 h 228 rdt4/ odt12 rx data reg4/ dsp data reg12 un- change d 16 w r 39 h 38 h d138 h 228 rdt5/ odt13 rx data reg5/ dsp data reg13 un- change d 16 w r 3b h 3a h d13a h 228 rdt6/ odt14 rx data reg6/ dsp data reg14 un- change d 16 w r 3d h 3c h d13c h 228 rdt7/ odt15 rx data reg7/ dsp data reg15 un- change d 16 w r 3f h 3e h d13e h 228 table 59 dma mailbox register map (cont ? d) register description reset value bit dsp acces s dma / p acc. p msb addr. p lsb addr. dsp addr. page no.
peb 20570 peb 20571 register description data sheet 160 2001-03-19 preliminary table 60 clock generator register map reg name access address reset value comment page no. cpdc r/w d080 h 0000 h pdc control 232 cpfs r/w d081 h 0001 h pfs control 233 clkout r/w d082 h 0008 h clkout control 234 crefsel r/w d083 h 0000 h dcxo reference clock selection 235 crefclk r/w d084 h 0003 h refclk control 236 cdcl2 r/w d085 h 0004 h dcl_2000 control 236 cdcl r/w d086 h 000b h dcl control 238 cfsc r/w d087 h 0002 h fsc control 239 cl1clk r/w d088 h 0000 h l1_clk control 240 cpfssy r/w d089 h 0000 h pfs synchronization mode 241 crtcnt r d08e h 0000 h real-time counter 242 cstrap r/w d08f h xxxx xxxx xxxx xx10 b strap status register 243
peb 20570 peb 20571 register description data sheet 161 2001-03-19 preliminary 6.2 detailed register description 6.2.1 transiu register description 6.2.1.1 transiu iom-2000 configuration register ticr register read/write address: d0a0 h reset value: 0000 h note: the reset value of bit 4kfsc is undefined, since this read-only bit is toggled every 250 s. note: ? x ? = unused (read as ? 0 ? ) 15 14 13 12 11 10 9 8 xxxxxxxx 76543210 x x x 4kfsc cmden dxen dr1 dr0 dr1..0 iom-2000 data rate and channel number 00 = 3.072 mbit/s data rate; 8 iom-2000 channels are supported 01 = 6.144 mbit/s data rate; 16 iom-2000 channels are supported 10 = 12.288 mbit/s data rate; 24 iom-2000 channels are supported 11 = reserved dxen dx line enable 0 = iom-2000 dx line to the vip is in tri-state 1 = iom-2000 dx line to the vip is enabled (starting with the next 4 khz frame) cmden cmd line enable 0 = iom-2000 cmd line to the vip is in tri-state 1 = iom-2000 cmd line to the vip is enabled (starting with the next 4 khz frame) 4kfsc 4 khz fsc (read only) 0 = in the transiu, the current 8 khz iom-2000 frame starts in the second half of the current 4 khz u pn of s/t frame 1 = in the transiu, the current 8 khz iom-2000 frame starts in the first half of the current 4 khz u pn of s/t frame
peb 20570 peb 20571 register description data sheet 162 2001-03-19 preliminary 6.2.1.2 transiu channel configuration registers the channel registers are used for iom-2000 channel disabling and mode programming. each iom-2000 channel may be programmed to u pn , lt-s, or lt-t mode, or completely disabled. important only four channels out of eight channels are programmable to u pn and s/t modes in vip peb 20590, the remaining four channels may be operated as u pn transceiver only. it is the user ? s responsibility to ensure that the iom-2000 channels in the transiu are correctly configured in order to match with the line configuration of the vip see below: registers tccr0 - 2 read/write address: tccr0: d0a1 h tccr1: d0a2 h tccr2: d0a3 h reset values: ffff h table 61 available isdn modes for each vip channel vip_0,1,2 channel 01234567 transiu channel 0 8 16 1 9 17 2 10 18 3 11 19 4 12 20 5 13 21 6 14 22 7 15 23 available vip mode u pn u pn s/t u pn u pn s/t u pn u pn s/t u pn u pn s/t available vip8 mode u pn s/t u pn s/t u pn s/t u pn s/t u pn s/t u pn s/t u pn s/t u pn s/t 15 14 13 12 11 10 9 8 c7m(1:0) c6m(1:0) c5m(1:0) c4m(1:0) 76543210 c3m(1:0) c2m(1:0) c1m(1:0) c0m(1:0)
peb 20570 peb 20571 register description data sheet 163 2001-03-19 preliminary note: tccr0 (channel 7..0), tccr1 (channel 15..8) and tccr2 (channel 23..16) have the same structure, only tcrr1 is shown here. note: iom-2000 cha. 0 and 1 are restricted to the modes lt-s and u pn . this means that tccr0:c0m1..0 and tccr0:c1m1..0 must not be programmed to the value 01. c7..0m(1:0) operational mode of iom-2000 channel7..0 00 = channel is configured to s mode (lt-s) 01 = channel is configured to s mode (lt-t) 10 = channel is configured to u pn mode 11 = channel is disabled, ? 0 ? s are sent on the dx line
peb 20570 peb 20571 register description data sheet 164 2001-03-19 preliminary 6.2.1.3 vip command registers (vipcmr0, vipcmr1, vipcmr2) the vipcmr0-2 registers contain command information dedicated to the vip 0, 1, 2 (only the vipcmr0 is shown here, vipcmr1 and vipcmr2 have the same structure). vipcmr register write address: vipcmr0: d0a8 h vipcmr1: d0a9 h vipcmr2 h : d0aa h reset value: 0000 h 15 14 13 12 11 10 9 8 x x x x rd_n pllpps sh_fsc delre 76543210 delch(2:0) exref refsel (2:0) wr_n wr_n write command to vip_n (s/t, u pn ) 0 = data sent to vip_n is invalid 1 = data sent to vip_n is valid refsel(2:0) reference clock channel select (lt-t) the reference clock signal for the delic oscillator is generated from the internal vip_n channel_m coded in these 3 bits and passed on via pin refclk to the next cascaded vip or directly to the delic 000 = reference clock provided by channel_0 001 = reference clock provided by channel_1 ... 007 = reference clock provided by channel_7 exref external reference clock selection (lt-t)
peb 20570 peb 20571 register description data sheet 165 2001-03-19 preliminary 0 = no external reference clock source. reference clock is generated from internal vip_n channel specified in refclk(2:0) and passed on via refclk pin to vip_n-1 or directly to delic. 1 = reference clock is generated from external source via pin inclk and passed on via refclk pin to vip_n-1 or directly to delic. the internal reference clock generation logic is disabled. note that vip_0 has the highest priority in terms of clock selection delch(2:0) delay measurement channel selection (u pn ) selects one of the eight u pn line interface channels of each vip where the delay is to be measured. 000 = delay is measured in u pn channel_0 001 = delay is measured in u pn channel_1 ... 111 = delay is measured in u pn channel_7 delre delay counter resolution (u pn ) resolution of the delay counter. 0 = resolution of 65 ns (15.36 mhz period) 1 = resolution of 130 ns (7.68 mhz period) note: using a resolution of 65 ns, the maximum delay of 20.8 s is not covered (refer to delay(7:0) bits) sh_fsc short fsc pulse 0 = the next fsc frame is no superframe 1 = the next fsc is assumed as superframe pllpps pll positive pulse sensing 0 = normal operation 1 = the clock recovering plls of all vip channels operate on positive line pulses only rd_n read request to vip status register s_n (s/t, u pn ) 0 = no register read
peb 20570 peb 20571 register description data sheet 166 2001-03-19 preliminary note: unused bits (x) read as ? 0 ? . the registers are reset upon every 8 khz frame sync to avoid multiple data transmit/receive to/from the vip. 1 = the dsp reads the vip register (during initialization, debugging or error conditions). the register value is available for the read operation in the consecutive frame (after the next fsc). note: to avoid blocking, the dsp must not issue this bit during normal operation.
peb 20570 peb 20571 register description data sheet 167 2001-03-19 preliminary 6.2.1.4 vip status registers the vipstr0-2 registers contain the status bits received from the dedicated vip for vips 0, 1, 2 respectively (all three registers have the same structure). vipstr register read address: vipstr0: d0ac h , vipstr1: d0ad h , vipstr2: d0ae h reset value: 0000 h note: unused bits (x) read as ? 0 ? . 15 14 13 12 11 10 9 8 x x x x x vipvnr(1..0) x 76543210 delay(7:0) delay(7:0) line delay value (u pn ) returns the value of the measured line delay (in s) between the u pn transmit and receive frame with a resolution of 65 ns or 130 ns (programmable in vipcmr.delre bits). the value indicates the delay between the transmitted m-bit and the received lf-bit (minus the u pn guard time of 2 bits). the delay for one direction equals to the measured delay divided by two. the channel address for the delay measurement is coded in vipcmr.delch(2:0) bits. the vip provides 2 values in one u pn frame (one every 125 s) from which the bigger one is the valid. note: the transceiver delays of the vip are included in the delay measurement. vipvnr(1..0) vip version number 0 = vip version v1.1 1 = vip version v2.1
peb 20570 peb 20571 register description data sheet 168 2001-03-19 preliminary 6.2.1.5 transiu initialization channel command register the initialization channel command register contains the command bits for vip_n, channel_m together with 5 bits of the vip channel address. the vip only acts upon the command bits if they were declared valid by the delic issuing a write command. bit wr is dedicated to the command bits of groups conf1, conf2 and tst2, whereas wr_st informs the vip about changes in the layer 1 state machine of the delic (smini(2:0) and msync bits). the delic may also explicitly read the vip ? s status information by issuing bit rd. the reset value of each bit is ? 0 ? except bits mode(2:0) which are set to ? 011 ? note: a read command to the vip must not be issued during normal operation to avoid a loss of information when the vip is reporting status information at the same time. ticcmr register write address: ls-word: d0b0 h , ms-word: d0b1 h reset value: 0000 h 31 30 29 28 27 26 25 24 x vipadr(1:0) chadr(2:0) fil exlp 23 22 21 20 19 18 17 16 plls pd dhen x fil1 pdown loop tx_en 15 14 13 12 11 10 9 8 pllint aac(1:0) bbc(1:0) owin(2:0) 76543210 mf_en mode(2:0) mosel(1:0) rd wr wr write command (s/t, u pn ) 0 = data sent in these bits is invalid 1 = all configuration bits contain valid data note: does not apply to smini(2:0) and msync bits rd read request to vip command bits (s/t, u pn ) 0 = normal operation
peb 20570 peb 20571 register description data sheet 169 2001-03-19 preliminary 1 = delic read request of the ticcmr register which was sent to the vip. it includes initialization and configuration commands and the channel addresses. the vip returns these values (instead of sending the actual vip status information) within the iom-2000 stat_n_m bit stream. the values are available in the next frame (after next fsc) in delic ticstr register. note: to avoid blocking, the delic must not issue this bit during normal operation . mosel(1:0) interface mode selection (s/t, u pn ) 00 = channel programmed to s/t mode 01 = channel programmed to u pn mode 10 = reserved 11 = reserved mode(2:0) mode configuration (s/t, u pn ) 001 = channel programmed to lt-t mode note: iom-2000 cha. 0 and 1 are restricted to the modes lt-s and u pn . this means that mode(2..0) must not be programmed to the value 001 for these channels. also see section 3.2.4.2 on page 58 . 011 = channel programmed to lt-s mode (point-to-point or extended passive bus configuration) or u pn mode 111 = channel programmed to lt-s mode (short passive bus mode) note: all other states are reserved. the reset value is 011, e.g. the default mode of vip is lt-s mf_en multiframe enable (s/t) 0 = multiframes are disabled 1 = multiframes are enabled owin(2:0) oversampling window size (s/t, u pn ) specifies the width of the oversampling window in bit samples. the window is centered about the middle of the bit. for example, a size of 16 means that, upon detection of (16/2) = 8 times logical ? 1 ? , the received bit is detected as ? 1 ? . the window size is programmed in steps of two as shown below: 000 = 2 001 = 4 010 = 6
peb 20570 peb 20571 register description data sheet 170 2001-03-19 preliminary ... 111 = 16 bbc(1:0) balancing bit control (u pn ) 00 = adaptive generation of balancing bit (depending on line delay). upon reception of info3 or info4 10 = balancing bit control is disabled, and no balancing bit is added 11 = balancing bit control is disabled, and balancing bit is added after each code violation in the m-bit (info3 or info4) aac(1:0) adaptive amplifier control (s/t, u pn ) 00 = adaptive amplifier control in vip is enabled. the amplifier and the equalizer are switched on/off depending on the level of the received line signal with respect to the comparator threshold. 10 = adaptive amplifier control is disabled. the amplifier and the equalizer are switched off permanently. 11 = adaptive amplifier control is disabled. the amplifier and the equalizer are switched on permanently pllint receive pll integrator (u pn ) 0 = programmable deviation disabled 1 = programmable deviation enabled, i.e., the rxpll reacts only after a certain number of consequent deviations from the pll controlling range. tx_en transmitter enable (s/t, u pn ) 0 = transmitter (analog line driver) is disabled (e.g. for non- transparent analog loops in lt-t) 1 = transmitter is enabled (e.g. for switching of transparent analog loops in lt-s) loop loop-back mode in vip enable (s/t, u pn ) 0 = loops disabled 1 = loop-back enabled. channel_m transmit data is looped back to the receive data path (either transparent or non-transparent according to state of bit tx_en). depending on bit exlp the loop is closed internally or externally. note: for u pn additionally bit tutlr:utn has to be set to enable the test loop in the delic (n= iom-2000 channel number) pdown power down mode (s/t, u pn )
peb 20570 peb 20571 register description data sheet 171 2001-03-19 preliminary 0 = operational mode 1 = channel_m in power-down mode (only the level detector in the vip receiver is in operational mode) dhen d-channel handling enable (lt-t) 0 = d-channel transmitted transparently, without any condition 1 = d-channel transmitted transparently if no collision is detected (e=d), if collision is detected (e d) ? 1s ? are transmitted in d- channel fil1 test filter enable (applicable only in vip v2.1 and higher versions) 0 = test filter disable (default setting) 1 = test filter enable (only for test purpose) pd phase deviation selection (lt-t) 0 = phase deviation = (2 bits - 2 oscillator periods + analog delay) 1 = phase deviation = (2 bits - 4 oscillator periods + analog delay) plls receive pll adjustment (s/t, u pn ) 0 = tracking step equals 0.5 oscillator period 1 = tracking step equals 1.0 oscillator period exlp external loop (s/t, u pn ) 0 = no external analog loop. if bit loop=1 the loop is closed internally 1 = external analog loop. if bit loop=1 the loop is closed externally fil filter enable (u pn only) 0 = filter of equalizer inside the vip receiver disabled 1 = filter of equalizer inside the vip receiver enabled chadr(2:0) channel_m address for commands 000 = command word is dedicated to vip_n channel_0 001 = command word is dedicated to vip_n channel_1 010 = command word is dedicated to vip_n channel_2 011 = command word is dedicated to vip_n channel_3 100 = command word is dedicated to vip_n channel_4 101 = command word is dedicated to vip_n channel_5 110 = command word is dedicated to vip_n channel_6
peb 20570 peb 20571 register description data sheet 172 2001-03-19 preliminary note: unused bits (x) read as ? 0 ? . 111 = command word is dedicated to vip_n channel_7 vipadr(2:0) vip_n address for commands 00 = command word is dedicated to vip_0 01 = command word is dedicated to vip_1 10 = command word is dedicated to vip_2 11 = reserved
peb 20570 peb 20571 register description data sheet 173 2001-03-19 preliminary 6.2.1.6 transiu initialization channel status register (ticstr) the initialization channel status register contains the command bits to vip_n, channel_m mirrored by the vip in response to a read command issued by the delic in the previous frame. note: the actual status information from the vip channels is stored in the data ram to make it accessible for the delic layer-1 state machine software in the dsp. ticstr register read address: ls-word: d0b2 h , ms-word: d0b3 h reset value: 0000 h 31 30 29 28 27 26 25 24 x vipadr(1:0) chadr(2:0) fil exlp 23 22 21 20 19 18 17 16 plls pd dhen x x pdown loop tx_en 15 14 13 12 11 10 9 8 pllint aac(1:0) bbc(1:0) owin(2:0) 76543210 mf_en mode(2:0) mosel(1:0) rd wr
peb 20570 peb 20571 register description data sheet 174 2001-03-19 preliminary 6.2.1.7 up test loop register the up test loop register allows to switch an analog loop in the vip for test purposes. tutlr register read/ write address: ls-word: d0b4 h , ms-word: d0b5 h reset value: 0000 h note: when a channel is programmed to up loop back test-mode, the transiu expects the frame-start in the receive direction to be detected with very small delay after the frame-start in the transmit direction, and not after 125 us or more (as in normal work mode). note: to enable the loop in the vip, additionally ticcmr:loop must be set to 1 for the respective channel. 31 30 29 28 27 26 25 24 xxxxxxxx 23 22 21 20 19 18 17 16 ut(23:16) 15 14 13 12 11 10 9 8 ut(15:8) 76543210 ut(7:0) ut(n) up loop back bit for iom-2000 channel n 0 = up channel is set to normal mode 1 = up channel is set to loop back test mode in the vip
peb 20570 peb 20571 register description data sheet 175 2001-03-19 preliminary 6.2.1.8 scrambler mode register scmod register read/write address: d010 h reset value: 0003 h 15 14 13 12 11 10 9 8 xxxxxxxx 76543210 x x x x x scmod2 scmod1..0 scmod1..0 scrambling mode of the u pn line interface 00 = scrambling according to itu-t v.27 01 = scrambling compatible to octat-p peb 2096 10 = dasl scrambler 11 = no scrambling scmod2 scrambler/ descrambler indication mode (only valid in delic v2.3 and higher versions) 0 = no "scrambling finished" indication is provided descrambling is initiated following fsc rising edge 1 = "scrambling finished" indication is provided by register scsta. descrambling is initiated by writing to register scsta
peb 20570 peb 20571 register description data sheet 176 2001-03-19 preliminary 6.2.1.9 scrambler status register scsta register read/write address: d011 h reset value: undefined note: scrambling and descrambling will only work correctly if (in the initialization phase) bit 8 of the oak register st2 is set to ? 1 ? (see ? ghdlcu frame frequency ? on page 213.) 15 14 13 12 11 10 9 8 xxxxxxx x 7654321 0 x x x x x x scsta1 scsta0 scsta0 descrambler status 0 = write access: start of descrambling algorithm for all channels enabled in the hram (only valid if bit scmod2 = 1!) read access: descrambler is processing data 1 = write access: start of scrambling algorithm for all channels enabled in the hram read access: descrambling is finished scsta1 scrambler status (only valid if bit scmod2 = 1) 0 = read access: scrambler is processing data 1 = read access: scrambling is finished
peb 20570 peb 20571 register description data sheet 177 2001-03-19 preliminary 6.2.2 iomu register description 6.2.2.1 iomu control register icr register read/write address: d040 h reset value: 02 h 15 14 13 12 11 10 9 8 xxxxxxxx 76543210 xxicdbaoddc dr(1:0) icdb idle current d-buffer (for test purpose; only if iomu is in idle mode: icr:a = ? 0 ? ) 0 = make frame buffer 0 accessible to the dsp 1 = make frame buffer 1 accessible to the dsp a iomu activation 0 = the iomu is idle. the state machine of the iomu is idle, and no accesses to the i-buffer are executed by the iomu. 1 = the iomu is active, and works according to the programming of the other control register bits. od dd0 and dd1 output mode 0 = push-pull mode. 1 = open-drain mode dc double data rate clock 0 = single clock (dcl frequency is identical to the iom-2 data rate) 1 = double clock (dcl frequency is double the iom-2 data rate) dr(1:0) iom-2 data rate 00 = iom-2 data rate of 1 x 384 kbit/s (1 x 6 time slots/frame) 01 = iom-2 data rate of 1 x 768 kbit/s (1 x 12 time slots/frame) 10 = iom-2 data rate of 2 x 2.048 mbit/s (2 x 32 time slots/frame) (default) 11 = iom-2 data rate of 1 x 4.096 mbit/s (1 x 64 time slots/frame)
peb 20570 peb 20571 register description data sheet 178 2001-03-19 preliminary 6.2.2.2 iomu status register isr register read address: d041 h reset value: undefined note: (x) unused bits read as ? 0 ? 15 14 13 12 11 10 9 8 ibuffxxxxxxx 76543210 xxxxxxxx ibuff i-buffer index note: used for testing. may also be used in double data rate mode of the iomu to determine if the iomu buffers have been swapped already 0 = buffer 0 is currently used as i-buffer, buffer 1 is used as d-buffer 1 = buffer 1 is currently used as i-buffer, buffer 0 is used as d-buffer
peb 20570 peb 20571 register description data sheet 179 2001-03-19 preliminary 6.2.2.3 iomu tri-state control register itscr register read/write address: set address: d042 h reset address: d043 h read address: d044 h reset value: 00 h 15 14 13 12 11 10 9 8 ts(15:8) 76543210 ts(7:0) ts(15:0) every bit determines whether dd0/1 output is in tri-state during the time slot sequence. the time slot sequence length, indices and port controlled by each ts-bit is defined according the iomu data rate mode (icr.dr(1:0)) 0 = dd0/1 is in tri-state during the related time slot sequence 1 = dd0/1 is driven by the iomu during the related time slot sequence
peb 20570 peb 20571 register description data sheet 180 2001-03-19 preliminary table 62 tristate control assignment for iom-2 time slots itscr bit 1 x 6 ts/frame 1 x 12 ts/frame 2 x 32 ts/frame 1 x 64 ts/frame dd0 ts dd0 ts dd0/1 ts dd0/1 ts ts0 dd0 0 dd0 0 dd0 0-3 dd0 0-3 ts1 dd0 1 dd0 1 dd0 4-7 dd0 4-7 ts2 dd0 2 dd0 2 dd0 8-11 dd0 8-11 ts3 dd0 3 dd0 3 dd0 12-15 dd0 12-15 ts4 dd0 4 dd0 4 dd0 16-19 dd0 16-19 ts5 dd0 5 dd0 5 dd0 20-23 dd0 20-23 ts6 not used dd0 6 dd0 24-27 dd0 24-27 ts7 not used dd0 7 dd0 28-31 dd0 28-31 ts8 not used dd0 8 dd1 0-3 dd0 32-35 ts9 not used dd0 9 dd1 4-7 dd0 36-39 ts10 not used dd0 10 dd1 8-11 dd0 40-43 ts11 not used dd0 11 dd1 12-15 dd0 44-47 ts12 not used not used dd1 16-19 dd0 48-51 ts13 not used not used dd1 20-23 dd0 52-55 ts14 not used not used dd1 24-27 dd0 56-59 ts15 not used not used dd1 28-31 dd0 60-63
peb 20570 peb 20571 register description data sheet 181 2001-03-19 preliminary 6.2.2.4 iomu drdy register idrdyr register read address: d045 h reset value: undefined note: in 1 x 4.096 mbit/s mode (i.e.16 iom-2 channels/frame), drdy is sampled only during the d-channels of the first eight iom-2 channels of every frame. 15 14 13 12 11 10 9 8 00000000 76543210 ds(7:0) bit drdy sample dsx indicates the availability of the d-channels of the previous frame. 0 = stop (d-channel blocked due to collision), 1 = go e.g. ds1 was sampled during the d-channel of iom-2 channel 1, etc. ds0 corresponds to d-channel of iom-2 port 0 cha 0 ds1 corresponds to d-channel of iom-2 port 0 cha 1 ds2 corresponds to d-channel of iom-2 port 0 cha 2 ds3 corresponds to d-channel of iom-2 port 0 cha 3 ds4 corresponds to d-channel of iom-2 port 0 cha 4 ds5 corresponds to d-channel of iom-2 port 0 cha 5 ds6 corresponds to d-channel of iom-2 port 0 cha 6 ds7 corresponds to d-channel of iom-2 port 0 cha 7
peb 20570 peb 20571 register description data sheet 182 2001-03-19 preliminary 6.2.2.5 iomu data prefix register idpr register read/write address: d046 h reset value: e0 h note: (x) unused bits read as ? 0 ? 15 14 13 12 11 10 9 8 idp(7:0) 76543210 xxxxxxxx idp(7:0) iomu data prefix determines the high byte of every word being read from the iom circular- buffer (i-buffer or d-buffer). the low byte is the data being read from the circular buffer. after reset this register contains the msb of the base address of the a-law- to-linear rom table: e0 h .
peb 20570 peb 20571 register description data sheet 183 2001-03-19 preliminary 6.2.3 pcmu register description 6.2.3.1 pcmu command register pcr register read/write address: d060 h reset value: 0000 h note: ? x ? = unused (read as ? 0 ? ) 15 14 13 12 11 10 9 8 xxxxxxxx 76543210 x x sfh icdb pa pdcl pdr(1:0) pdr(1:0) pcm data rate 00 = 2.048 mbit/s (port 0..3) 01 = 4.096 mbit/s (port 0, 2) 10 = 8.092 mbit/s (port 0) 11 = 16.384 mbit/s (1 x 256 time slots per frame, if only first or second half of 8 khz frame is handled) (port 0) pdcl pcm double data rate clock 0 = single data rate clock 1 = double data rate clock pa pcmu activation 0 = the pcmu is in idle mode 1 = the pcmu is in active mode icdb idle current d-buffer used only for testing of pcmu in idle mode (pcr:pa = '0') to determine which buffer is being accessed by the dsp 0 = frame buffer 0 is accessed by the dsp 1 = frame buffer 1 is accessed by the dsp sfh second frame half applicable only in 16.384 mbit/s data rate mode 0 = the first 128 time slots of each frame are handled by the pcmu 1 = the second 128 time slots of each frame are handled by the pcmu
peb 20570 peb 20571 register description data sheet 184 2001-03-19 preliminary 6.2.3.2 pcmu status register psr register read address: d061 h reset value: undefined note: (x) unused bits read as ? 0 ? 15 14 13 12 11 10 9 8 pbuffxxxxxxx 76543210 xxxxxxxx pbuff p-buffer index note: used for testing. may also be used in double data rate mode of the pcmu to determine if the pcmu buffers have been swapped already 0 = buffer 0 is currently used as p-buffer, buffer 1 is used as d-buffer 1 = buffer 1 is currently used as p-buffer, buffer 0 is used as d-buffer
peb 20570 peb 20571 register description data sheet 185 2001-03-19 preliminary 6.2.3.3 pcmu tri-state control registers ptsc0 register read/write read address: d062-63 h (set/reset) set address: d062h reset address: d063h ptsc1 register read/write read address: d064-65 h (set/reset) set address: d064 h reset address: d065h ptsc2 register read/write read address: d066-67 h (set/reset) set address: d066 h reset address: d067 h ptsc3 register read/write read address: d068-69 h (set/reset) set address: d068 h reset address: d069 h ptsc4 register read/write read address: d06a-6b h (set/reset) set address: d06a h reset address: d06b h
peb 20570 peb 20571 register description data sheet 186 2001-03-19 preliminary ptsc5 register read/write read address: d06c-6d h (set/reset) set address: d06c h reset address: d06d h ptsc6 register read/write read address: d06e-6f h (set/reset) set address: d06e h reset address: d06f h ptsc7 register read/write read address: d070-71 h (set/reset) set address: d070 h reset address: d071 h reset values (ptsc0..7): 0000 h 15 14 13 12 11 10 9 8 ptscn(15:8) 76543210 ptscn(7:0) ptscn (15..0) tristate control for each pcm time slot 0 = the controlled time slot is invalid 1 = the controlled time slot is valid
peb 20570 peb 20571 register description data sheet 187 2001-03-19 preliminary 6.2.3.4 pcmu data prefix register pdpr register read/write address: d072 h reset value: e0 h note: (x) unused bits read as ? 0 ? 15 14 13 12 11 10 9 8 pdp(7:0) 76543210 xxxxxxxx pdp(7:0) pcmu data prefix the data written to this register is read as the most significant byte of every time slot read by the dsp from the pcmu frame buffers. can be used for quick access to the a/-law rom, for conversion of compressed data (received via the pcm interface) into linear value. after reset this register contains the msb of the base address of the a-law- to-linear rom table: e0 h . to enable quick conversion from -law to linear, the pcmu data prefix register should be programmed to e1 h .
peb 20570 peb 20571 register description data sheet 188 2001-03-19 preliminary 6.2.4 a-/-law unit register description 6.2.4.1 a/-law unit control register a/-law unit control register (amcr) read/write address: d020 h reset value: 0000 h note: ? x ? = unused bits this register controls the conversion mode of the a/-law unit 15 14 13 12 11 10 9 8 xxxxxxxx 76543210 xxxxxxxmode mode a/-law mode programming 0 = conversion from linear value to a-law value (default) 1 = conversion from linear value to -law value
peb 20570 peb 20571 register description data sheet 189 2001-03-19 preliminary 6.2.4.2 a/-law input register a/-law unit input register (amir) write address: d021 h reset value: undefined note: - in -law mode, only the 14 msbs are processed. - in a-law mode, only the 13 msbs are processed. 15 14 13 12 11 10 9 8 ind(15:8) 76543210 ind(7:0) ind(15:0) linear input data provides the linear input data that is to be converted into logarithmic data format according to a-law or -law algorithm.
peb 20570 peb 20571 register description data sheet 190 2001-03-19 preliminary 6.2.4.3 a/-law output register a/-law unit output register (amor) read address: d022 h reset value: undefined note: ? x ? = unused bits, driven to ? 0 ? 15 14 13 12 11 10 9 8 xxxxxxxx 76543210 outd(7:0) outd(7:0) logarithmic output data provides the logarithmic output data generated by the a/--law unit out of the linear input data. the data format (a-law or -law) depends on the the selected conversion algorithm.
peb 20570 peb 20571 register description data sheet 191 2001-03-19 preliminary 6.2.5 hdlcu registers description 6.2.5.1 hdlcu control register in order to enable dsp access all the buffers and rams, dspctrl bit must be set to ? 1 ? . hcr register write address: d180 h reset value: 0001 h note: each time dspctrl is set, hprs is also set. 15 14 13 12 11 10 9 8 x bitor x x x x x x 7654321 0 x hprs(5:0) dspctrl bitor determines the order of bits inside one hdlc data byte 0 = hdlc data is transmitted/ received with msb first (default) 1 = hdlc data is transmitted/ received with lsb first hprs(5:0) hdlcu channel preset the number of hdlc channels to be processed by the hdlcu dspctrl dsp access control to the hdlcu 0 = the dsp must not access the hdlcu buffers and rams 1 = the dsp may access the hdlcu buffers
peb 20570 peb 20571 register description data sheet 192 2001-03-19 preliminary 6.2.5.2 hdlcu status register hsta register read address: d180 h reset value: 0001 h 15 14 13 12 11 10 9 8 hhold bitor x chcnt(5:1) 76543210 chcnt(0) hprs(5:0) dspctrl dspctrl dsp access control to the hdlcu 0 = the hdlcu is currently processing the channel 1 = the dsp is currently accessing the hdlcu hprs(5:0) hdlc channel preset number of hdlc channels handled by the hdlcu (max. 32) chcnt(5:0) channel count number of channels that have already been processed in the current frame bitor bitorder determines the order of bits inside an hdlc data byte going to (coming from) the iomu, pcmu or transiu. 0 = hdlc data is transmitted with msb first 1 = hdlc data is transmitted with lsb first hhold hdlcu busy indicator 0 = hdlcu is processing the current frame 1 = hdlcu has finished processing the current frame
peb 20570 peb 20571 register description data sheet 193 2001-03-19 preliminary 6.2.5.3 channel command vector hccv registers read/ write address: 4040 h - 405f h each of the 32 hdlc channels has a 7-bit command vector that resides in the corresponding address of the command ram. the structure of a command vector is as follows: note: accesses to these registers are possible only if register bit hcr:dspctrl = 1 ? x ? = unused 15 14 13 12 11 10 9 8 xx x xxxxx 7 6 5 43210 x dbsel recres txcmd(2:0) crc idle dbsel d- or b-channel select 0 = indication for a b-channel. hdlc protocol is performed on all 8 data bits 1 = indication for a d-channel. hdlc protocol is performed only on the 2 msb data bit in the receive input buffer and transmit output buffer recres receiver reset 0 = normal operation 1 = reset the hdlc receiver txcmd(2:0) transmit command 000= end transmission 001= start transmission at the first bit of the d-channel 010= start transmission at the second bit of the d-channel 011= start transmitting a flag (beginning with the fifth bit of the flag, since ? 0111 ? is automatically inserted) 100= abort transmission note: other combinations are reserved crc crc enable 0 = crc checking algorithm off
peb 20570 peb 20571 register description data sheet 194 2001-03-19 preliminary note: in the receive direction, the only function of the command vector is to indicate whether the channel is a d-channel or a b-channel, and whether to use crc decoding or not. the main function of the command vector is to control the flow of time slots in the transmit direction. 1 = crc checking algorithm on idle inter frame timefill idle mode 0 = transmit ? ones ? over an idle channel (no shared flag are possible in this mode) 1 = transmit ? flags ? over an idle channel (shared flags are supported )
peb 20570 peb 20571 register description data sheet 195 2001-03-19 preliminary 6.2.5.4 channel status vector hcsv registers read addresses: 40a0 h - 40bf h reading a channel from the receive output buffer and writing to a channel in the transmit input buffer is done according to the channel ? s status vector in the transmit output buffer. this vector contains 7 flags: note: accesses to these registers are possible only if register bit hcr:dspctrl = 1 ? x ? = not used 15 14 13 12 11 10 9 8 xxxxxxxx 76543210 x flag empty full abort stop crc no no not octet 0 = normal operation 1 = the last bits of a message have not filled an octet (8 bits) crc crc error 0 = no crc error in received message 1 = crc error was detected in the received message stop stop indication 0 = normal operation 1 = hdlcu has detected an end of message flag in the receive direction. the dsp must read the octet in the receive output buffer before the next message start flag is detected abort abort indication 0 = normal operation 1 = the dsp has detected an incoming abort message (7 consecutive ? 1s ? ). the stop flag is also set to 1. this means that the dsp should ignore the current message being transmitted over the channel in question and report to the external micro controller full receive buffer full indication
peb 20570 peb 20571 register description data sheet 196 2001-03-19 preliminary 0 = normal operation 1 = indicates that the receive output buffer has a newly processed octet in it. the dsp must read this octet before starting the next processing session, otherwise it might be lost. empty transmit buffer empty 0 = the transmit buffer is full. 1 = the transmit buffer is empty. the current time slot in the transmit input buffer has been fully processed by the hdlcu. the transmit input buffer is ready to receive the next octet of the message by the dsp. note: the dsp must put a new octet into the buffer before starting the next processing session, otherwise the same octet will be read again. flag status vector flag 0 = ignore the status vector and do not read or write on this channel 1 = read the channel ? s status vector and process accordingly note: flag will go to ? 1 ? as soon as empty or full go to ? 1 ? .
peb 20570 peb 20571 register description data sheet 197 2001-03-19 preliminary 6.2.6 ghdlc register description 6.2.6.1 ghdlc test/ normal mode register gtest register read/write address: d0c0 h reset value: 0001 h note: as gtest has a reset value of 01h this register has to set to 0 to enable the ghdlcu 15 14 13 12 11 10 9 8 x xxxxxxx 7 6543210 x xxxxxxtest chmod1..0 channel mode 0 = normal operation mode 1 = test mode
peb 20570 peb 20571 register description data sheet 198 2001-03-19 preliminary 6.2.6.2 ghdlc channel mode register gchm register read/write address: d0c1 h reset value: 0000 h 15 14 13 12 11 10 9 8 x xxxxxxx 7 6543210 x xxxxxchmod(1..0) chmod1..0 channel mode 00 = channel 0 used for up to 8.192 mhz (delic-pb only) channel 0 used for up to 2.048 mhz (delic-lc) ghdlc buffer size = 32 bytes 01 = 2 channels (ch 0+3) used for up to 2.048 mhz ghdlc buffer size = 2 x 16 bytes note: delic-pb only 10 = 4 channels (ch 0..3) used up to 2.048 mhz ghdlc buffer size = 4 x 8 bytes note: delic-pb only 11 = reserved
peb 20570 peb 20571 register description data sheet 199 2001-03-19 preliminary 6.2.6.3 ghdlc interrupt register gint register read address: d0d4 h reset value: 0000 h note: int0-int3 are reset by a read access to this register note: for gchm:chmod = 00 (cha. 0 up to 8 mbit/s) only int0 is used for gchm:chmod = 01 (cha. 0 and 3 up to 2 mbit/s) only int0, int3 are used. for gchm:chmod = 10 (cha. 0..3 up to 2 mbit/s) all bits are used 15 14 13 12 11 10 9 8 xxxxxxxx 76543210 xxxxint3int2int1int0 intn bits interrupt indication for ghdlc channel n (= 0..3) 0 = normal operation 1 = ghdlc interrupt has occurred
peb 20570 peb 20571 register description data sheet 200 2001-03-19 preliminary 6.2.6.4 ghdlc fsc interrupt control register gfint register read address: d0d3 h reset value: 0000 h note: the interrupt frequency can be set in register st2 ( chapter 6.2.6.15 ). 15 14 13 12 11 10 9 8 xxxxxxxx 76543210 xxxxfint3fint2fint1fint0 fintn fsc interrupt control ghdlc channel n (= 0..3) 0 = the rising edge of a 62.5 s/ 10s frame causes a receiver interrupt only if a full interrupt has not occurred during the previous frame 1 = the rising edge of a 62.5 s/ 10s frame causes a receiver interrupt regardless whether or not a full interrupt occurred during the previous frame
peb 20570 peb 20571 register description data sheet 201 2001-03-19 preliminary 6.2.6.5 ghdlc receive channel status registers 0..3 grsta register 0 read address: d0c2 h grsta register 1 read address: d0c3 h grsta register 2 read address: d0c4 h grsta register 3 read address: d0c5 h reset value: 001f h 15 14 13 12 11 10 9 8 xxxxxxcolldunder 76543210 empty over full rbfill(4:0) rbfill(4:0) receive buffer fill indicates to the dsp the currently available number of bytes - 1 in the receive buffer full receive buffer full 0 = no receive buffer full indication 1 = receive buffer block of the ghdlc is full. the blocks have been switched. over buffer overrun 0 = no buffer overrun indication 1 = two consecutive full interrupts were received without a ghdlc access to the status register in between, i.e. a buffer was missed. empty transmit buffer empty 0 = no transmit buffer empty indication 1 = the transmit buffer block currently being transmitted over the ghdlc channel has been emptied under buffer underrun 0 = no buffer underrun indication 1 = a buffer containing an incomplete message has been emptied without a continuation of the message in the other buffer
peb 20570 peb 20571 register description data sheet 202 2001-03-19 preliminary note: reading the register grsta resets its bits to the default value. colld collision detected 0 = no collision detection indication 1 = collision detected during transmission. the message needs to be re-sent. note: only relevant in hdlc-mode, if one device does not operate conform to the hdlc protocol definition
peb 20570 peb 20571 register description data sheet 203 2001-03-19 preliminary 6.2.6.6 ghdlc receive data and status to each data byte in the receive buffer 4 flag bits are appended rxdat registers read address: 2040 h -207f h 15 14 13 12 11 10 9 8 abort end crc no x x x x 76543210 rdat7..0 no not octet 0 = received message is a multiple of eight bits 1 = received message is not a multiple of eight bits crc crc error flag 0 = received byte contains no crc error flag. 1 = received byte contains a crc error flag. a crc error was detected in the received frame. end end flag 0 = received byte contains no end flag 1 = received byte contains an end flag abort abort flag 0 = received byte contains no abort flag 1 = received byte contains an abort flag rd7..0 received data byte
peb 20570 peb 20571 register description data sheet 204 2001-03-19 preliminary 6.2.6.7 ghdlc mode registers gmod register 0 read/write address: d0c6 h gmod register 1 read/write address: d0c7 h gmod register 2 read/write address: d0c8 h gmod register 3 read/write address: d0c9 h reset value: 0140 h 15 14 13 12 11 10 9 8 x x x x gem gedge edge te 76543210 class colld ppod iftf opmod(1:0) crcmod(1:0) crcmod (1:0) crc mode 00 = crc algorithm disabled 01 = 16-bit crc algorithm (x 16 +x 12 +x 5 +1) 10 = 32-bit crc algorithm (x 31 +x 26 +x 23 +x 22 +x 16 +x 12 +x 11 +x 10 +x 8 +x 7 +x 5 +x 4 +x 2 +x 1 +1) 11 = reserved opmod(1:0) operational mode programs the mode of the ghdlc channel note: every channel of ghdlc, that is not in use, should be programmed to async mode (opmod = "10"), in order to prevent any access of the idled channels to the ghdlc buffers. for example, if ghdlc channel mode register chmod = "00" (operation only of channel 0) then opmod field in registers gmod 1/2/3 should be set to "10" (async mode) 00 = hdlc mode 01 = extended transparent mode 10 = asynchronous mode (enables accesses to register gasync) 11 = reserved iftf interframe time fill 0 = sequence of ? 1s ? is used as interframe time fill characters
peb 20570 peb 20571 register description data sheet 205 2001-03-19 preliminary 1 = flags (7e h ) are used as interframe time fill characters ppod push-pull / open-drain configuration 0 = open-drain 1 = push-pull colld collision detection 0 = collision detection disabled 1 = arbitration between several ghdlc on a bus is done using collision detection class priority class assignment 0 = channel has priority class 8 1 = channel has priority class 10 te transmit enable 0 = transmit line is only enabled during the transmission of a message including opening and closing flags 1 = transmit line is always enabled edge edge programming for receive data sampling 0 = receiver samples data on rising edge of the line clock 1 = receiver samples data on falling edge of the line clock gedge edge programming for ghdlc receive data sampling 0 = receiver samples data on rising edge of the line clock 1 = receiver samples data on falling edge of the line clock gem ghdlc enhanced mode 0 = normal operation gedge is disabled, edge is used for sampling the data. 1 = enhanced operation gedge is enabled, edge has to be programmed to the opposite of gedge. note: the enhanced mode ensures proper handling of interframe time fill (itf) flags with shared ? 0 ? (please refer to figure 50 ). in enhanced operation an additional delay of 15 s is added to the received data.
peb 20570 peb 20571 register description data sheet 206 2001-03-19 preliminary 6.2.6.8 ghdlc channel transmit command registers gtcmd register 0 write address: d0ca h gtcmd register 1 write address: d0cc h gtcmd register 2 write address: d0ce h gtcmd register 3 write address: d0d0 h reset value: 0000 h 15 14 13 12 11 10 9 8 xxxxxxxx 76543210 x stop txcmd tbfill(4:0) tbfill(4:0) transmit buffer fill indicates to the ghdlc unit the currently available number of bytes - 1 in the transmit buffer. txcmd transmission command 0 = transmission is not started 1 = start transmission stop stop command 0 = message continues in the next buffer 1 = end of the message is in this buffer
peb 20570 peb 20571 register description data sheet 207 2001-03-19 preliminary 6.2.6.9 async control register gasync register read/ write address: d0d2 h reset value: 0000 accesses to register gasync: accesses to the different bits of this register are only possible in async mode of the corresponding ghdlc channel (see ? ghdlc mode registers ? on page 204.). note: ghdlc channels 3,2,1 are only accessible, if the respective bits in register muxctrl are set. 15 14 13 12 11 10 9 8 xx x xxxxx 76 5 43210 ioport(7..0) ioport bits writing a "1" to the bit position sets the port pin below reading from the bit position indicates the current state of the port pin below bit 0 ltxd0 lrxd0 bit 1 ltxd1 lrxd1 bit 2 ltxd2 lrxd2 bit 3 ltxd3 lrxd3 bit 4 lrts0 lcts0 bit 5 lrts1 lcts1 bit 6 lrts2 lcts2 bit 7 lrts3 lcts3
peb 20570 peb 20571 register description data sheet 208 2001-03-19 preliminary 6.2.6.10 lclk0 control register lclk0 control register (glclk0) read/write address: d08a h reset value: 0000 h note: ? x ? = unused bits, read as 0 . 15 14 13 12 11 10 9 8 xxxxx xxx 76543 210 x x x x x lclk0en lclk0(1:0) lclk0en lclk0 output enable 0 = lclk0 is input (default) 1 = lclk0 is driven outward via lclk0 pin lclk0(1:0) lclk0 output clock rate note: this option is valid only when lclk0 is output. when lclk0 is input the frequency is determined externally. 00 = 2.048 mhz (default) 01 = 4.096 mhz 10 = 8.192 mhz 11 = 16.384 mhz
peb 20570 peb 20571 register description data sheet 209 2001-03-19 preliminary 6.2.6.11 lclk1 control register lclk1 control register (glclk1) read/write address: d08b h reset value: 0000 h note: ? x ? = unused bits, read as 0 . 15 14 13 12 11 10 9 8 xxxxx xxx 76543 210 x x x x x lclk1en lclk1(1:0) lclk1en lclk1 output enable 0 = lclk1 is input (default) 1 = lclk1 is driven outward via lclk1 pin lclk1(1:0) lclk1 output clock rate note: this option is valid only when lclk1 is output. when lclk1 is input the frequency is determined externally. 00 = 2.048 mhz (default) 01 = 4.096 mhz 10 = 8.192 mhz 11 = 16.384 mhz
peb 20570 peb 20571 register description data sheet 210 2001-03-19 preliminary 6.2.6.12 lclk2 control register lclk2 control register (glclk2) read/write address: d08c h reset value: 0000 h note: ? x ? = unused bits, read as 0 . 15 14 13 12 11 10 9 8 xxxxx xxx 76543 210 x x x x x lclk2en lclk2(1:0) lclk2en lclk2 output enable 0 = lclk2 is input (default) 1 = lclk2 is driven outward via lclk2 pin lclk2(1:0) lclk2 output clock rate note: this option is valid only when lclk2 is output. when lclk2 is input the frequency is determined externally. 00 = 2.048 mhz (default) 01 = 4.096 mhz 10 = 8.192 mhz 11 = 16.384 mhz
peb 20570 peb 20571 register description data sheet 211 2001-03-19 preliminary 6.2.6.13 lclk3 control register lclk3 control register (glclk3) read/write address: d08d h reset value: 0000 h note: ? x ? = unused bits, read as 0 . 15 14 13 12 11 10 9 8 xxxxx xxx 76543 210 x x x x x lclk3en lclk3(1:0) lclk3en lclk3 output enable 0 = lclk3 is input (default) 1 = lclk3 is driven outward via lclk3 pin lclk3(1:0) lclk3 output clock rate note: this option is valid only when lclk3 is output. when lclk3 is input the frequency is determined externally. 00 = 2.048 mhz (default) 01 = 4.096 mhz 10 = 8.192 mhz 11 = 16.384 mhz
peb 20570 peb 20571 register description data sheet 212 2001-03-19 preliminary 6.2.6.14 muxes control register muxctrl register oak: read/write address: d14a h reset value: 0000 h 15 14 13 12 11 10 9 8 x xxxxxxx 7 6543210 x x x x x pmux1 pmux0 imux imux 0 = iom-2000 pins are used for the iom-2000 interface 1 = iom-2000 pins are used for the ghdlc cha. 1 pmux0 0 = pcm ports 0 & 2 pins are used for pcm 1 = pcm ports 0 & 2 pins are used for ghdlc cha. 2 pmux1 0 = pcm ports 1 & 3 pins are used for pcm 1 = pcm ports 1 & 3 pins are used for ghdlc cha. 3
peb 20570 peb 20571 register description data sheet 213 2001-03-19 preliminary 6.2.6.15 ghdlcu frame frequency st2 register oak: write address: dsp-register reset value: xxxx xx00 xxxx xxxx b 15 14 13 12 11 10 9 8 x x x x x x ouser1 ouser0 7 654321 0 x xxxxxx x ouser1 0 = 16 khz ghdlcu frame frequency 1 = 96 khz ghdlcu frame frequency ouser0 0 = test mode write access to hram-0 is enabled write access to hram-1, hram-2 is disabled 1 = write access to hram0, hram-1, hram-2 is enabled 1) 1) this bit has to be set once during initialization for single scrambling mode. if mixed scrambling mode is used (e.g. dasl/octat-p) the following has to be done: when accessing the hram this bit has to be reset ( ? 0 ? ) before enabling descrambler/scrambler it has to be set ( ? 1 ? ).
peb 20570 peb 20571 register description data sheet 214 2001-03-19 preliminary 6.2.7 dcu register description 6.2.7.1 interrupt mask register imask register read/write address: d002 h reset value: 0000 h note: the unused bits (x) are read as ? 0 ? . 15 14 13 12 11 10 9 8 xxxxxxxx 76543210 xxxxxxximask imask ghdlc interrupt mask 0 = ghdlc interrupt disabled 1 = ghdlc interrupt enabled
peb 20570 peb 20571 register description data sheet 215 2001-03-19 preliminary 6.2.7.2 status event register steve register read address: d003 h reset value: 0000 h note: unused bits ( ? x ? ) are read as ? 0 ? . 15 14 13 12 11 10 9 8 xxxxxxxx 76543210 xxxxxpfsfscfp pfs pfs status bit 0 = normal operation 1 = pfs rising edge has occurred (reset by dsp read access) fsc fsc status bit 0 = normal operation 1 = fsc rising edge has occurred (reset by dsp read access) fp fsc & pfs status bit 0 = normal operation 1 = both fsc and pfs rising edges have occurred, i.e. bits pfs and fsc are set (reset by dsp read access)
peb 20570 peb 20571 register description data sheet 216 2001-03-19 preliminary 6.2.7.3 statistics counter register statc register read/write address: d004 h reset value: unchanged reset value: unchanged upon chip reset, but reset upon fsc detection if statc was read by the dsp since last occurence of fsc. note: the unused bits (x) are read as ? 0 ? . 15 14 13 12 11 10 9 8 xxxxxxxx 76543210 statc(7:0) statc (7:0) statistics counter value
peb 20570 peb 20571 register description data sheet 217 2001-03-19 preliminary 6.2.7.4 statistics register stati register read/write address: d005 h reset value: 0000 h note: the unused bits (x) are read as ? 0 ? . 15 14 13 12 11 10 9 8 xxxxxxxx 76543210 msc(7:0) msc(7:0) max. statistics count
peb 20570 peb 20571 register description data sheet 218 2001-03-19 preliminary 6.2.8 p configuration registers 6.2.8.1 p interface configuration register mcfg register dsp: read dsp address: d148 h p: read/write p high address: none p low address: 48 h reset value: 00 h 15 14 13 12 11 10 9 8 xxxxxxxmode 76543210 drqlv irqlv irqmo imask iack pec fb dma dma dma mode enabled 0 = no dma 1 = dma enabled fb fly-by mode 0 = memory-to-memory mode used for dma transfers 1 = fly-by mode used for dma transfers pec pec transfers enable 0 = no pec transfers 1 = pec transfers are supported (for connection of c16x p) iack interrupt acknowledge mode 0 = interrupt vector is provided to cpu after 1st iack pulse. 1 = interrupt vector is provided to cpu after 2nd iack pulse. imask interrupt mask 0 = ireq pin is disabled 1 = ireq pin is enabled irqmo ireq pin mode 0 = open-drain mode
peb 20570 peb 20571 register description data sheet 219 2001-03-19 preliminary 1 = push-pull mode irqlv ireq pin level 0 = low active 1 = high active drqlv dreqr/dreqt pins level 0 = high active 1 = low active mode p interface mode contains the value of mode input pin sampled by rising edge of reset note: this signal is hardwired. 0 = intel/siemens mode 1 = motorola mode
peb 20570 peb 20571 register description data sheet 220 2001-03-19 preliminary 6.2.8.2 interrupt vector register ivec register dsp: read/ write dsp address: d168 h p: read p high address: none p low address: 68 h reset value: unchanged 76543210 ivec(7:0) ivec7..0 interrupt vector contains the interrupt vector address that is output during an inta cycle of the p
peb 20570 peb 20571 register description data sheet 221 2001-03-19 preliminary 6.2.9 p mailbox registers description 6.2.9.1 p command register mcmd register dsp: read dsp address: d140 h p: write p address: 40 h reset value: 00 h 76543210 mcmd mcmd p command contains the p command (8-bit opcode) to the delic.
peb 20570 peb 20571 register description data sheet 222 2001-03-19 preliminary 6.2.9.2 p mailbox busy register mbusy register dsp: write dsp address: d141 h p: read p high address: 41 h p low address: none reset value: 00 h 15 14 13 12 11 10 9 8 mbusyxxxxxxx 76543210 xxxxxxxx mbusy p mailbox busy bit 0 = mailbox is available for the external p. the p may write a command to mcmd. 1 = mailbox is blocked for the external p. the p may not write a command to mcmd. note: mbusy is automatically set each time a command is written to mcmd by the p. mbusy is reset automatically by a direct oak write operation to the mbusy register.
peb 20570 peb 20571 register description data sheet 223 2001-03-19 preliminary 6.2.9.3 p mailbox generic data register mgen register dsp: read dsp address: d144 h dsp high: d143 h dsp low: d142 h p: write p high: 43 h p low: 42 h reset value: unchanged 15 14 13 12 11 10 9 8 mgen(15..8) 76543210 mgen(7..0) mgen (15..0) p mailbox generic data (16 bits)
peb 20570 peb 20571 register description data sheet 224 2001-03-19 preliminary 6.2.9.4 p mailbox (general and dma mailbox) data registers mdtn register (n=0..7) dsp: read addr. see table on page 156 tdtn/ mdtn+8 register (n=0..7) p: write reset value: unchanged note: the 16 data registers (mdt1..7, tdt0/mdt8..tdt7/mdt15) have the same structure. the addresses are displayed in the register map ( page 156 , page 158 ). 15 14 13 12 11 10 9 8 mdtn(15..8) 76543210 mdtn(7..0) mdtn (15..0) p mailbox data (each byte is addressed separately by the external p)
peb 20570 peb 20571 register description data sheet 225 2001-03-19 preliminary 6.2.9.5 dsp command register ocmd register dsp: write dsp address: d160 h p: read p address: 60 h reset value: 00 h 76543210 ocmd ocmd dsp command contains the dsp command/ indication (8-bit opcode) to the delic.
peb 20570 peb 20571 register description data sheet 226 2001-03-19 preliminary 6.2.9.6 dsp mailbox busy register obusy register dsp: read dsp address: d161 h p: read/ write p high address: 61 h p low address: none reset value: 00 h 15 14 13 12 11 10 9 8 obusyxxxxxxx 76543210 xxxxxxxx obusy dsp mailbox busy bit 0 = mailbox is available for the dsp. the dsp may write a command/ indication ocmd. 1 = mailbox is blocked for the dsp. the dsp may not write a command/ indication to ocmd. note: obusy is automatically set each time a command/ indication is written to ocmd by the dsp. obusy is reset automatically by a direct p write operation to the obusy register
peb 20570 peb 20571 register description data sheet 227 2001-03-19 preliminary 6.2.9.7 dsp mailbox generic data register ogen register dsp: write dsp address: d164 h dsp high: d163 h dsp low: d162 h p: read p high: 63 h p low: 62 h reset value: unchanged 15 14 13 12 11 10 9 8 ogen(15..8) 76543210 ogen(7..0) ogen 15..0 dsp mailbox generic data (16 bits)
peb 20570 peb 20571 register description data sheet 228 2001-03-19 preliminary 6.2.9.8 dsp mailbox (general and dma mailbox) data registers odtn register (n= 0..15) dsp: write addr. on page 158 rdtn/ odtn+8 register (n=0..7) p: read reset value: unchanged ( note: the 16 data registers (odt1..7, rdt0/odt8..rdt7/odt15) have the same structure. the addresses are displayed in the register map ( page 156 , page 158 ). 15 14 13 12 11 10 9 8 odtn(15..8) 76543210 odtn(7..0) odtn (15..0) dsp mailbox data (each byte is addressed separately by the external p)
peb 20570 peb 20571 register description data sheet 229 2001-03-19 preliminary 6.2.10 dma mailbox registers description 6.2.10.1 dma mailbox transmit counter register dtxcnt register dsp: read/write address: d150 h reset value: 000f h note: writing to txcnt initiates a dma transfer of txcnt+1 bytes to the dma tx mailbox. txcnt is decremented with every dma cycle. when all bytes have been transmitted txcnt has the value ? f ? . 15 14 13 12 11 10 9 8 xxxxxxxx 76543210 xxxx txcnt(3:0) txcnt(3..0) number of bytes to be transmitted minus 1
peb 20570 peb 20571 register description data sheet 230 2001-03-19 preliminary 6.2.10.2 dma mailbox receive counter register drxcnt register dsp: read/write address: d170 h reset value: 000f h note: writing to rxcnt initiates a dma transfer of rxcnt+1 bytes to the dma rx mailbox. rxcnt is decremented with every dma cycle. when all bytes have been transmitted rxcnt has the value ? f ? . 15 14 13 12 11 10 9 8 xxxxxxxx 76543210 xxxx rxcnt(3:0) rxcnt(3..0) number of bytes to be received minus 1
peb 20570 peb 20571 register description data sheet 231 2001-03-19 preliminary 6.2.10.3 dma mailbox interrupt status register dinsta register dsp: read/ write address: d152 h reset value: 0000 h contains the status of the dma mailbox. the bits in this register are reset by a read access to register dinsta. 15 14 13 12 11 10 9 8 xxxxxxxx 76543210 xxxxtintrinttmskrmsk tint transmit interrupt from dma mailbox (read only) 0 = no transmit interrupt from dma-mailbox occurred 1 = the dma-controller has finished to write the requested number of bytes to the dma-mailbox. rint receive interrupt from dma mailbox (read only) 0 = no transmit interrupt from dma-mailbox occurred 1 = the dma-controller has finished to read the requested number of bytes from the dma-mailbox. tmsk transmit interrupt mask (read/ write) 0 = disable transmit interrupt 1 = enable transmit interrupt rmsk receive interrupt mask (read/ write) 0 = disable receive interrupt 1 = enable receive interrupt
peb 20570 peb 20571 register description data sheet 232 2001-03-19 preliminary 6.2.11 clock generator register description 6.2.11.1 pdc control register pdc control register (cpdc) read/write address: d080 h reset value: 0000 h note: ? x ? = unused bits, read as 0 . 15 14 13 12 11 10 9 8 xxxxxxxx 76543210 xxxxxx pdc(1:0) pdc(1:0) pdc frequency selection (only in master mode when pdc is output) 00 = pdc = 2.048 mhz (default) 01 = pdc = 4.096 mhz 10 = pdc = 8.192 mhz 11 = pdc = 16.384 mhz
peb 20570 peb 20571 register description data sheet 233 2001-03-19 preliminary 6.2.11.2 pfs control register pfs control register (cpfs) read/write address: d081 h reset value: 0001 h note: ? x ? = unused bits, read as 0 . note: when the pfs is output, its frequency is always 8 khz, therefore this bit should be left in its reset-value ('1') and not to be changed. the direction of pfs and pdc: input (slave) or output (master) is determined by the master/slave strap (dreqr pin) during reset. 15 14 13 12 11 10 9 8 xxxxxxxx 76543210 xxxxxxxpfs pfs pfs frequency selection (selectable in slave mode when pfs is input; in master mode pfs = 8 khz) 0 = pfs = 4 khz 1 = pfs = 8 khz (default)
peb 20570 peb 20571 register description data sheet 234 2001-03-19 preliminary 6.2.11.3 clkout control register clkout control register (clkout) read/write address: d082 h reset value: 0008 h note: ? x ? = unused bits, read as 0 . 15 14 13 12 11 10 9 8 xxxx x xxx 7654 3 210 xxxxclkouten clkout clkouten clkout pin enable 0 = clkout pin is in tri-state. 1 = clkout pin is active. (default) clkout clkout pin frequency 000 = 2.048 mhz 001 = 4.096 mhz (default) 010 = 8.192 mhz 011 = 15.36 mhz 100 = 16.384 mhz
peb 20570 peb 20571 register description data sheet 235 2001-03-19 preliminary 6.2.11.4 dcxo reference clock select register refsel register (crefsel) read/write address: d083 h reset value: 0000 h note: ? x ? = unused bits, read as 0 this register controls the selection of the source of the dcxo 8khz reference clock 15 14 13 12 11 10 9 8 xxxxxxxx 76543210 xxxxrefsel en refsel(2:0) refselen dcxo reference clock enable 0 = the reference clock is disabled (default) 1 = the reference clock is enabled refsel(2:0) dcxo reference clock select 000 = dxclk/192 (default) 001 = xclk/256 010 = xclk 011 = refclk (when input) 100 = refclk (when input)/64 101 = pfs (when input)
peb 20570 peb 20571 register description data sheet 236 2001-03-19 preliminary 6.2.11.5 refclk control register refclk control register (crefclk) read/write address: d084 h reset value: 0003 h note: ? x ? = unused bits, read as 0. refclk may be configured as an input or as an output. when configured as an input, it may be used as a source for the on-chip dcxo 8khz reference clock. this option is handled by the dcxo reference clock select register (crefsel). when configured as an output it is derived from xclk input pin. in order to drive refclk, xclk may be divided by 256, 192, 4, 3 or 1. 15 14 13 12 11 10 9 8 xxxx x xxx 7654 3 210 x x x x refclken refdiv(2:0) refclken refclk pin output enable 0 = refclk is input, the pad is not output enabled 1 = refclk is output refdiv(2:0) refclk pin output divider selection this determines the value by which the xclk maximum clock of 2.048 mhz is divided internally. 000 = division by 256 001 = division by 192 010 = division by 4 011 = division by 3 (default) 100 = division by 1
peb 20570 peb 20571 register description data sheet 237 2001-03-19 preliminary 6.2.11.6 dcl_2000 control register dcl_2000 control register (cdcl2) read/write address: d085 h reset value: 0004 h note: ? x ? = unused bits, read as 0 . 15 14 13 12 11 10 9 8 xxxxxxxx 76543210 xxxxxdcl2endcl2(1:0) dlc2en dcl_2000 clock enable 0 = dcl_2000 clock is disabled 1 = dcl_2000 clock is enabled (default) dcl2(1:0) dcl_2000 clock rate 00 = 3.072 mhz (default) 01 = 6.144 mhz 10 = 12.288 mhz
peb 20570 peb 20571 register description data sheet 238 2001-03-19 preliminary 6.2.11.7 dcl control register dcl control register (cdcl) read/write address: d086 h reset value: 000b h note: ? x ? = unused bits, read as 0 . 15 14 13 12 11 10 9 8 xxxxxxxx 76543210 xxxxdclen dcl(2:0) dclen dcl clock enable 0 = dcl is disabled 1 = dcl is enabled (default) dcl(2:0) dcl clock rate 000 = 384 khz 001 = 768 khz 010 = 1536 khz 011 = 2048 khz (default) 100 = 4096 khz
peb 20570 peb 20571 register description data sheet 239 2001-03-19 preliminary 6.2.11.8 fsc control register fsc control register (2) read/write address: d087 h reset value: 0002 h note: ? x ? = unused bits, read as 0 . 15 14 13 12 11 10 9 8 xxxxxxxx 76543210 xxxxifscdefscdfscenfscsh fscen fsc clock enable 0 = fsc is disabled (stuck at '0') 1 = fsc is enabled (default) fscsh short fsc pulse 0 = the next fsc pulse will be longer than 2 dcl cycles (default) 1 = the next fsc pulse will be shorter than 2 dcl cycles (short fsc) efscd external fsc delay 0 = no delay between fsc and dcl rising edge (recommended for vip v2.1 and higher) 1 = fsc rising edge is delayed by one clk61 clock (16 ns) relative to dcl/ dcl2000 (suitable only for vip up to v1.1) ifscd internal fsc delay (only valid if cstrap: bit0 = 1) 0 = no delay between fsc and dcl rising edge (default) 1 = fsc rising edge is delayed by one clk61 clock (16 ns) relative to dcl/ dcl2000 (only for test purpose) note: if only one short fsc pulse is needed, this bit should be reset to '0' by the delic software, after the next fsc rising edge detection (after the beginning of the next frame). it is not executed automatically by the hardware.
peb 20570 peb 20571 register description data sheet 240 2001-03-19 preliminary 6.2.11.9 l1_clk control register l1_clk control register (cl1clk) read/write address: d088 h reset value: 0000 h note: ? x ? = unused bits, read as 0 . 15 14 13 12 11 10 9 8 xxxxxx x x 765432 1 0 x x x x x x l1clkdis l1clk l1clken l1_clk disable 0 = l1_clk is enabled (default) 1 = l1_clk is disabled l1clk l1_clk clock rate 0 = 7.68 mhz (default) 1 = 15.36 mhz
peb 20570 peb 20571 register description data sheet 241 2001-03-19 preliminary 6.2.11.10 pfs sync register pfs sync register (cpfssy) read/write address: d089 h reset value: 0000 h note: ? x ? = unused bits, read as 0. pfssync has to written once during initialization (value don ? t care) to bring the rising edge of fsc close to pfs. note: pfs and fsc are not exactly aligned. see ? ac characteristics ? on page 249 for more information. 15 14 13 12 11 10 9 8 xxxxxxxx 76543210 x x x x pfssync(1:0)
peb 20570 peb 20571 register description data sheet 242 2001-03-19 preliminary 6.2.11.11 real-time counter register rt counter register (crtcnt) read address: d08e h reset value: 0000 h this 18-bit counter counts 8 khz cycles. it is used by the software to time the handling of required tasks. one period of the counter (counting from 0000h to ffffh and back to 0000h) is 32.768 sec. only the 16 msbs of the counter may be read by the oak, therefore the actual resolution is 0.5 ms.. 15 14 13 12 11 10 9 8 rtcount(15:8) 76543210 rtcount(7:0) rtcount(15:0) the 16 msbs of the real-time counter
peb 20570 peb 20571 register description data sheet 243 2001-03-19 preliminary 6.2.11.12 strap status register strap status register (cstrap) read/ write address: d08f h reset value: 0000 0xxx xxxx xx10 b note: ? x ? = unused bits, read as 0 note: . 15 14 13 12 11 10 9 8 xxxxx strap(10:8) 7654321 0 strap(7:0) strap (10:0) this register enables the oak to read the straps values, as sampled during reset bit 10 pcm clock master strap bit 9:7 test mode strap bit 6 emulation boot strap bit 5 pll bypass strap bit 4 dsp pll power-down strap bit 3 boot strap bit 2 reset counter bypass strap bit 1 dcxo fast-synchronization enable (read/write) 0 = 1 = linear (slow) synchronization (for dect applications) fast synchronization (default) bit 0 internal source clock strap (read/ write) 0 = 1 = pfs, pdc, dcl, fsc, dcl2000 are delayed by some ns (default) pfs, pdc, dcl, fsc, dcl2000 are not delayed
peb 20570 peb 20571 package outlines data sheet 244 2001-03-19 preliminary 7 package outlines p-tqfp-100-3 (plastic thin quad flat package) gpm05247 smd = surface mounted device sorts of packing package outlines for tubes, trays etc. are contained in our data book ? package information ? . dimensions in mm
peb 20570 peb 20571 electrical characteristics and timing diagrams data sheet 245 2001-03-19 preliminary 8 electrical characteristics and timing diagrams 8.1 absolute maximum ratings note: stresses above those listed here may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. parameter symbol limit values unit storage temperature t stg ? 65 to 150 c ic supply voltage v dd ? 0.3 to 4.6 v dc input voltage (except i/o) v i ? 0.3 to 6.0 v dc output voltage (including i/o); output in high or low state v o ? 0.3 to v dd + 0.3 v dc output voltage (including i/o); output in tri-state v i, v o ? 0.3 to 6.0 v esd robustness 1) hbm: 1.5 k ? , 100 pf 1) according to mil-std 883d, method 3015.7 and esd ass. standard eos/esd-5.1-1993. the pins (tbd) are not protected against voltage stress > (tdb) v (versus v s or gnd). the (tbd) performance prohibits the use of adequate protective structures. v esd,hbm 2000 v
peb 20570 peb 20571 electrical characteristics and timing diagrams data sheet 246 2001-03-19 preliminary 8.2 operating range note: in the operating range, the functions given in the circuit description are performed. parameter symbol limit values unit min. max. power supply voltage v dd 3.13 3.47 v ground v ss 00v voltage applied to input pins v in 05.5v voltage applied to output or i/o pins outputs enabled outputs high-z v out v out 0 0 v dd 5.5 v v operating temperature peb t a 070 c input transition rise or fall time ? t/ ? v010ns/v
peb 20570 peb 20571 electrical characteristics and timing diagrams data sheet 247 2001-03-19 preliminary 8.3 dc characteristics note: the listed characteristics are ensured over the operating range of the integrated circuit. typical characteristics specify mean values expected over the production spread. if not otherwise specified, typical characteristics apply at t a = 25 c and the given supply voltage. parameter symbol limit values unit test condition min. max. high-level input voltage v ih 2.0 v dd + 3. 3 1) 1) max. value < 5.5 v vv out >= v oh (min) low-level input voltage v il ? 0.3 0.8 v v out <= v ol (max) high-level output voltage (all pins except dd0, dd1, dx, ltxd0, txd0, txd1) v oh 2.4 v v dd = min, i oh = ? 2 ma low-level output voltage (all pins except dd0, dd1, dx, ltxd0, txd0, txd1) v ol 0.4 v v dd = min, i ol =2 ma high-level output voltage (pins dd0, dd1, dx, ltxd0, txd0, txd1) v oh 2.4 v v dd = min, i oh = ? 7 ma low-level output voltage (pins dd0, dd1, dx, ltxd0, txd0, txd1) v ol 0.4 v v dd = min, i ol =7 ma input leakage current i il 1 a v dd =3.3v, gnd = 0 v; all other pins are floating; v in =0v output leakage current i oz 1 a v dd =3.3v, gnd = 0 v; v out =0v avg. power supply current i init i cc (av) i ap 2) 2) power supply current for an application with 6 digital and 2 analogue phones including switching. 266.5 272.6 275 ma v dd =3.3v, t a =25 c: pdc = 8 mhz dsp @ 61.44 mhz
peb 20570 peb 20571 electrical characteristics and timing diagrams data sheet 248 2001-03-19 preliminary 8.4 capacitances 8.5 recommended 16.384 mhz crystal parameters parameter symbol limit values unit notes min. max. input capacitance i/o capacitance c in c i/o 7 7 pf pf f c =1 mhz, the pins, which are not under test, are connected to gnd output capacitance c out 10 pf crystal input capacitance (pin clk16-xi) c xin 3.3 pf crystal output capacitance (pin clk16-xo) c xout 3.3 pf parameter symbol limit values unit test condition min. max. motional capacitance c 1 25 ff shunt capacitance c 0 7pf external load capacitance c l 15 pf resonance resistance r r 30 ? frequency calibration tolerance 150 ppm
peb 20570 peb 20571 electrical characteristics and timing diagrams data sheet 249 2001-03-19 preliminary 8.6 ac characteristics 8.6.1 dma access timing the exact behavior required from every p interface signal during a dma access, determined according to the following modes: 1. motorola/intel mode: determined by the mode input pin. 2. normal/fly-by mode: programmable mode, in the control register of the p-interface. in any mode, the dack input alone is used to indicate that this is a dma transaction, and to select the dma mail-box. an activation of cs is not required in such cases. 8.6.1.1 dma access timing in motorola mode in this mode ds is used for timing the access, while r/w is used to distinguish between dma read transactions and dma write transactions. the r/w input signal is used differently in normal mode and in fly-by mode. the next table details the way in which r/w should be used in each mode, during dma transactions: in fly-by mode r/w is used inverted, because the same signal, r/w , is required for concurrent accessing of an external memory device. table 63 r/w behavior during dma transactions in normal and in fly-by mode mode r/w = ? 0 ? r/w = ? 1 ? normal (non-fly-by) write dma transaction. (a response to dma transmitter request) read dma transaction. (a response to dma receiver request) fly-by read dma transaction. (a response to dma receiver request) write dma transaction. (a response to dma transmitter request)
peb 20570 peb 20571 electrical characteristics and timing diagrams data sheet 250 2001-03-19 preliminary table 64 dma transaction timing in motorola mode parameter symbol limit values unit test conditions min. max. dack setup time to ds falling edge t sas 7 ns output load capacity of 50 pf dack hold time after ds rising edge t hsa 5ns d-bus setup time to ds rising edge t sds 5ns d-bus hold time after ds rising edge t hsd 8ns dreqt/dreqr delay after ds falling edge t dsr 036ns r/w setup time to ds falling edge t srws 7ns r/w hold time after ds rising edge t hsrw 5ns ds pulse width and interval between ds pulses t ws 30 ns d-bus valid after ds falling edge t dsdv 022ns d-bus float (high impedance) after ds rising edge t dsdt 015ns
peb 20570 peb 20571 electrical characteristics and timing diagrams data sheet 251 2001-03-19 preliminary figure 59 dma write-transaction timing in motorola mode note: r/w is described in normal mode. in fly-by mode, r/w should be high during dma write transactions. ds dack r/w d dreqt t sas t hsa t sds t hsd t dsr t srws t ws t hsrw last byte t ws
peb 20570 peb 20571 electrical characteristics and timing diagrams data sheet 252 2001-03-19 preliminary figure 60 dma read-transaction timing in motorola mode note: r/w is described in normal mode. in fly-by mode, r/w should be low during dma read transactions. 8.6.1.2 dma access timing in intel/infineon mode in this mode r and w are used for timing the access and to determine whether it ? s a dma-read cycle or dma-write cycle. r and w input signals are used in opposite ways in normal mode and in fly-by mode. the next table details the way in which r and w should be used in each mode, during dma transactions: ds dack r/w d dreqr t sas t hsa t dsr t srws t ws t hsrw t dsdv t dsdt last byte t ws
peb 20570 peb 20571 electrical characteristics and timing diagrams data sheet 253 2001-03-19 preliminary in fly-by mode r and w are used inverted, because these signals are required also for concurrent accessing of an external memory device. table 65 r/w behavior during dma transactions in normal and in fly-by modes mode r = ? 1 ? , w = ? 0 ? r = ? 0 ? , w = ? 1 ? normal (non-fly-by) write dma transaction. (a response to dma transmitter request) read dma transaction. (a response to dma receiver request) fly-by read dma transaction. (a response to dma receiver request) write dma transaction. (a response to dma transmitter request) table 66 dma transaction timing in intel/infineon mode parameter symbol limit values unit test conditions min. max. dack setup time to w or r falling edge t saw t sar 7 ns output load capacity of 50 pf dack hold time after w or r rising edge t hwa t hra 5ns d-bus setup time to w rising edge t sdw 5ns d-bus hold time after w rising edge t hwd 8ns dreqt/dreqr delay after w or r falling edge t dwr t drr 036ns w pulse width and interval between w pulses t ww 30 ns r pulse width and interval between r pulses t wr 30 ns d-bus valid after r falling edge t drdv 022 d-bus float (high impedance) after r rising edge t drdt 015
peb 20570 peb 20571 electrical characteristics and timing diagrams data sheet 254 2001-03-19 preliminary figure 61 dma write-transaction timing in intel/infineon mode note: the figure describes a transaction in normal mode. in fly-by mode, rd is used during dma write transactions, instead of wr . figure 62 dma read-transaction timing in intel/infineon mode note: the figure describes a transaction in normal mode. in fly-by mode, wr is used during dma read-transactions, instead of rd . wr (rd ) dack d dreqt t saw t hwa t sdw t hwd t dwr t ww last byte t ww rd (wr ) dack d dreqr t sar t hra t drr t drdv t drdt last byte t wr t wr
peb 20570 peb 20571 electrical characteristics and timing diagrams data sheet 255 2001-03-19 preliminary 8.6.2 p access timing p accesses delic by an activation of address and cs . 1. by driving the mode pin ? high ? the user chooses motorola work mode, by driving it ? low ? - intel/infineon work mode. the pin is sampled by reset rising edge. 2. moreover, there is a difference between work with multiplexed address/data bus and demultiplexed address and data buses (in intel/infineon mode). in motorola mode demultiplexed buses only used. the selection between multiplexed and demultiplexed is done by the manner of use of ale. 8.6.2.1 p access timing in motorola mode in this mode r/w distinguishes between read and write interactions, and ds is used for timing. note: ds x cs is active (low) when both, ds and cs , are active (low) table 67 timing for write cycle in motorola mode parameter symbol limit values unit notes min. max. r/w setup time before ds x cs rising edge t srws 17 ns output load capacity of 50 pf r/w hold time after ds x cs rising edge t hrws 5ns a-bus setup time before ds x cs rising edge t sas 22 ns a-bus hold time after ds x cs rising edge t has 6ns d-bus setup time before ds x cs rising edge t sds 5ns d-bus hold time after ds x cs rising edge t hds 8ns ds x cs pulse width t ws 17 ns
peb 20570 peb 20571 electrical characteristics and timing diagrams data sheet 256 2001-03-19 preliminary figure 63 write cycle motorola mode note: ds x cs is active (low) when both, ds and cs are active (low) table 68 timing for read cycle in motorola mode parameter symbol limit values unit notes min. max. r/w setup time before ds x cs falling edge t srws 0 ns output load capacity of 50 pf r/w hold time after ds x cs rising edge t hrws 5ns a-bus valid to d-bus valid t dad 028ns ds x cs falling edge to d-bus t dsd 028ns d-bus float after ds x cs rising edge t dsdh 016ns r/w a d ds x cs t srws t sas t sds t hrws t has t ws t hds
peb 20570 peb 20571 electrical characteristics and timing diagrams data sheet 257 2001-03-19 preliminary figure 64 read cycle motorola mode 8.6.2.2 p access timing in intel/infineon mode in this mode driving rd ? low ? causes read access, driving wr ? low ? causes write access. in order to work on demultiplexed bus ale has to be driven ? high ? all the time. table 69 timing for write cycle in intel/infineon demultiplexed mode parameter symbol limit values unit notes min. max. a-bus setup time before wr rising edge t saw 12 ns output load capacity of 50 pf a-bus hold time after wr rising edge t haw 5ns cs setup time before wr rising edge t scw 12 ns cs hold time after wr rising edge t hcw 5ns d-bus setup time before wr rising edge t sdw 6ns d-bus hold time after wr rising edge t hdw 8ns wr pulse width t ww 7ns a r/w dsxcs d t hsrw t srws t dsd t dad t dsdh
peb 20570 peb 20571 electrical characteristics and timing diagrams data sheet 258 2001-03-19 preliminary figure 65 write cycle intel/infineon demultiplexed mode note: rd x cs is active (low) when both, rd and cs are active (low) figure 66 read cycle intel/infineon demultiplexed mode table 70 timing for read cycle in intel/infineon demultiplexed mode parameter symbol limit values unit notes min. max. a-bus valid to d-bus valid t dad 0 28 ns output load capacity of 50 pf rd x cs falling edge to d-bus t drd 028ns d-bus float after rd x cs rising edge t drdh 016ns wr a cs d t sdw t saw t hdw t scw t haw t hcw t ww a rdxcs d t drd t dad t drdh
peb 20570 peb 20571 electrical characteristics and timing diagrams data sheet 259 2001-03-19 preliminary timing for multiplexed bus in this mode ale pin is used in order to lock the address, driven over the multiplexed a/d bus. figure 67 write cycle intel/infineon multiplexed mode table 71 timing for write cycle in intel/infineon multiplexed mode parameter symbol limit values unit notes min. max. a-bus setup time before ale falling edge t sal 12 ns output load capacity of 50 pf a-bus hold time after ale falling edge t hal 5ns ale pulse width t wl 7ns cs setup time before wr rising edge t scw 14 ns cs hold time after wr rising edge t hcw 5ns d-bus setup time before wr rising edge t sdw 6ns d-bus hold time after wr rising edge t hdw 8ns ale hold time after wr rising edge t hlw 5ns wr pulse width t ww 7ns wr cs ad ale t sal t hal t scw t hcw t sdw t hdw t hlw t wl address data t ww
peb 20570 peb 20571 electrical characteristics and timing diagrams data sheet 260 2001-03-19 preliminary figure 68 read cycle in intel/infineon multiplexed mode 8.6.3 interrupt acknowledge cycle timing the ireq (interrupt request) output signal of the delic is activated as a result of a dsp writing operation to the ocmd register (oak mailbox command register). such an operation sets the oak mailbox busy bit (obusy), which drives directly the ireq output signal. the ireq signal may be masked, by programming the mask bit within the p- interface control register (upcr). the p may force the delic to drive the interrupt-vector over the data-bus, by activation (low) of the interrupt acknowledge input signal (iack ). in motorola mode an interrupt acknowledge cycle consists of one iack pulse, during which the interrupt vector is issued by the delic. in intel/infineon mode an interrupt acknowledge cycle consists of table 72 timing for read cycle in intel/infineon multiplexed mode parameter symbol limit values unit notes min. max. ale low before rd x cs falling edge t hrl 5 ns output load capacity of 50 pf ale hold time after rd x cs rising edge t hlr 5ns ale pulse width t wl 7ns a-bus setup time before ale falling edge t sal 12 ns a-bus hold time after ale falling edge t hal 5ns rd x cs falling edge to d-bus valid t drd 028ns d-bus float after rd x cs rising edge t drdh 016ns rdxcs ale ad t wl t sal t ha l t drdh t hlr t drd t hrl address data
peb 20570 peb 20571 electrical characteristics and timing diagrams data sheet 261 2001-03-19 preliminary two iack pulses, and the interrupt vector is issued as a response to the second one. the vector ? s source the oak mailbox vector register (ovec). the value stored in this register is determined by the oak, by writing operation. ireq is not deactivated by the iack pulses directly, but by p writing access to obusy. figure 69 interrupt acknowledge cycle timing in motorola mode figure 70 interrupt acknowledge cycle timing in intel/infineon mode table 73 interrupt acknowledge cycle timing parameter symbol limit values unit notes min. max. d-bus valid after iack falling edge t dadv 0 31 ns output load capacity of 50 pf d-bus float after iack rising edge t dadt 019ns iack pulse width t wa 25 ns interval between two iack pulses t ha 10 1) 1) valid only for intel/infineon mode. ns ireq delay after wr or ds t dwi 28 ns iack d t dadv t dadt vector iack d t dadv t dadt t wa t ha t wa vector
peb 20570 peb 20571 electrical characteristics and timing diagrams data sheet 262 2001-03-19 preliminary figure 71 ireq deactivation timing note: ireq is deactivated due to p write operation to obusy register. in motorola mode ds and cs together time the write access. in intel mode wr alone times the write access. for more details regarding the timing required during write access to the delic, refer to section 8.6.2. the other signals required for a write operation to obusy in each mode, are assumed to be driven appropriately. 8.6.4 iom-2 interface timing note: fsc and dcl are outputs of the delic. yet, dcl is used also in the delic for sampling and driving of the other signals of the iom-2 interface, and thus the timing of these signals is related to dcl. table 74 iom-2 interface timing parameter symbol limit values unit notes min. typ. max. du0/du1 setup time before dcl falling edge t udf 10 ns du0/du1 hold time after dcl falling edge t uhf 10 ns drdy setup time before dcl falling edge 1) 1) drdy is sampled only once during every iom-2 channel, with the first d-bit (d0). for more details refer to ? support of drdy signal from quat-s ? on page 103 t ydf 10 ns drdy hold time after dcl falling edge t yhe 10 ns dd0/dd1 delay after dcl rising edge t dde 7 27 ns output load capacity of 50 pf dd0/dd1 float after dcl rising edge t dfe 622ns dsxcs ireq t dwi wr
peb 20570 peb 20571 electrical characteristics and timing diagrams data sheet 263 2001-03-19 preliminary figure 72 iom-2 interface timing figure 73 drdy timing dcl fsc dd0/dd1 du0/du1 dd0/dd1 du0/du1 single data rate mode double data rate mode t dde t dfe t udf t uhf t dde t dfe t udf t uhf du0 drdy single data-rate dcl double data-rate dcl 1st bit 2nd bit t ydf t ydf t yhe t yhe
peb 20570 peb 20571 electrical characteristics and timing diagrams data sheet 264 2001-03-19 preliminary note: usually dsp-clock is generated internally by the internal pll, in a frequency of 61.44 mhz. if on the other hand a lower frequency clcok is provided via clk_dsp input pin, the frequency of dcl should not exceed the frequency of dsp-clock- frequency / 4 (dsp clcok frequency devided by 4), in order to guarantee a proper operation of the delic. figure 74 dcl timing iom-2 table 75 dcl (iom-2 data clock) timing parameter symbol limit values unit notes min. typ. max. dcl clock period t dcp 2.604 s dcl = 384 khz 1.302 s dcl = 768 khz 651 ns dcl = 1536 khz 488 ns dcl = 2048 khz 244 ns dcl = 4096 khz dcl duty cycle 48 50 52 % table 76 fsc (iom-2 and iom-2000 frame-sync) timing parameter symbo l limit values unit notes min. typ. max. fsc delay after dcl rising edge 1) t fde -10 10 ns output load capacity of up to 50 pf on both, pfs and dcl fsc clock period t fsc 125 s 8 khz fsc clock period high in a long-pulse fsc cycle 2) t hlc 112 112.5 113 s dcl t dcp
peb 20570 peb 20571 electrical characteristics and timing diagrams data sheet 265 2001-03-19 preliminary figure 75 fsc timing iom-2 fsc clock period high in a short-pulse fsc cycle 3) t hsc 2.5 2.604 2.7 s dcl = 384 khz 1.2 1.302 1.4 s dcl = 768 khz 640 651 660 ns dcl = 1536 khz 480 488 490 ns dcl = 2048 khz 235 244 255 ns dcl = 4096 khz 1) fsc rises and falls by dcl rising edge, and should be sampled with the falling edge of dcl, in the other chips, connected to the iom-2 interface of the delic. 2) in a long-pulse fsc cycle, fsc is generated with a 50% duty cycle. fsc clock period low is the complement of this parameter to 125 s. 3) in a short-pulse fsc cycle, fsc is high for exactly one cycle of dcl, thus it is dependent on the frequency of dcl. fsc clock period low is the complement of this parameter to 125 s. table 76 fsc (iom-2 and iom-2000 frame-sync) timing (cont ? d) parameter symbo l limit values unit notes min. typ. max. dcl fsc fsc short-pulse t fde t fde t fde t fde t fsc t fsc t hlc t hsc long-pulse
peb 20570 peb 20571 electrical characteristics and timing diagrams data sheet 266 2001-03-19 preliminary 8.6.5 pcm interface timing table 77 pcm interface timing parameter symb ol limit values unit notes min. typ. max. rxd0..3 setup time before pdc falling edge t rpf 10 ns rxd0..3 hold time after pdc falling edge t rhf 10 ns pfs setup time before pdc falling edge 1) 1) in 8 khz pfs - slave mode, pfs is sampled by pdc falling edge. the first pdc cycle in which fsc is sampled as logic-1 after a sampling of logic-0, is considered as the first cycle of the new pcm frame. also see ? pcm master/slave mode clocks selection ? on page 144 t psp 10 ns in slave mode, when pfs and pdc are inputs. pfs setup time before pdc rising edge 2) 2) in 4 khz pfs - slave mode, pfs is sampled by pdc rising edge. in order to work appropriately in this mode, pfs should be sampled as logic-1 only once every frame. the cycle in which pfs is sampled as logic-1 is considered as the first cycle of the new frame. also see ? pcm master/slave mode clocks selection ? on page 144 t ppr 10 ns pfs hold time after pdc falling edge 1) t hpf 10 ns pfs hold time after pdc rising edge 2) t hpr 10 ns pfs pulse width (high) 3) 3) inside the delic, pfs is also sampled by dsp-clock (61.44 mhz). since this clock (dsp-clock) is not visible for the user, a pulse width of more then one 61.44 mhz cycle is required, in order to guarantee an appropriate sampling. t ppw 25 ns pfs delay after pdc 4) t pdp -10 10 ns in master mode, when pfs and pdc are outputs. pfs clock period t pcp 125 s pfs duty cycle 48 50 52 % txd0..3 delay after pdc rising edge t tpf 2 19 ns txd0..3 txd0..3 float after pdc rising edge t tfr 220ns tsc0..3 delay after pdc rising edge t tdr 219ns
peb 20570 peb 20571 electrical characteristics and timing diagrams data sheet 267 2001-03-19 preliminary figure 76 pfs timing in slave mode (input pcm clocks) figure 77 pfs timing in master mode 4) in pcm master mode (pfs and pdc are in output mode) pfs rises with a rising edge of pdc, and it ? s designed to be sampled with the falling edge of pdc at any (slave) chip connected to the pcm interface. the first pdc cycle in which pfs is sampled as logic-1 after a sampling of logic-0, is considered as the first cycle of the new pcm frame. pdc pfs (8 khz) pfs (4 khz) t psp t ppr t hpr t hpf t ppw t ppw pdc pfs (8 khz) t pdp t pdp t pcp
peb 20570 peb 20571 electrical characteristics and timing diagrams data sheet 268 2001-03-19 preliminary figure 78 pfs interface timing table 78 pdc (pcm data clock) timing in master mode (output mode) parameter symbol limit values unit notes min. typ. max. pdc clock period t pcp 488 ns pdc = 2048 khz 244 ns pdc = 4096 khz 122 ns pdc = 8192 khz 61 ns pdc = 16384 khz pdc duty cycle t pdc 48 52 % pdc tsc0..3 txd0..3 rxd0..3 txd 0..3 rxd0..3 single data rate mode double data rate mode t tdr t tdr t tfr t tfr t tpf t tpf t rhf t rhf t rpf t rpf
peb 20570 peb 20571 electrical characteristics and timing diagrams data sheet 269 2001-03-19 preliminary note: usually dsp-clock is generated internally by the internal pll, in a frequency of 61.44 mhz. if on the other hand a lower frequency clcok is provided via clk_dsp input pin, the frequency of pdc (input or output) should not exceed the frequency of dsp-clock-frequency / 4 (dsp clcok frequency devided by 4), in order to guarantee a proper operation of the delic. figure 79 pdc parameters table 79 pdc timing in input mode note: the minimum pulse width (high or low) of pdc depends on the dsp clock frequency. usually this clock is generated internally by the internal pll, in a frequency of 61.44 mhz. in this case the values in the table above are valid. if a lower frequency for dsp-clock is provided via clk_dsp input pin, and pdc is used as input, the low/high pulse width of pdc should not be smaller then 1.5 x dsp-clock-cycle (dsp-clock-cycle is the cycle time of the provided dsp clock). figure 80 pdc timing in input mode parameter symbol limit values unit notes min. typ. max. pdc minimum high pulse t pmh 22 ns in input mode pdc minimum low pulse t pml 22 ns in input mode pdc t pcp pdc t pmh t pml
peb 20570 peb 20571 electrical characteristics and timing diagrams data sheet 270 2001-03-19 preliminary 8.6.6 iom-2000 interface timing table 80 iom-2000 interface timing parameter symbo l limit values unit notes min. typ. max. dr setup time before dcl_2000 falling edge t dsf 1ns dr hold time after dcl_2000 falling edge t dhf 12 ns dx delay after dcl_2000 rising edge t xdr 20 ns stat setup time before dcl_2000 falling edge t ssf 1ns stat hold time after dcl_2000 falling edge t shf 12 ns cmd delay after dcl_2000 rising edge t cdr 20 ns fsc rising edge delay after dcl_2000 rising edge 1) (in both, long and short pulse fsc cycles) 1) fsc is the same pin used for the iom-2 interface ( table 76 ). fsc rises with a rising edge of dcl_2000, and it ? s designed to be sampled with the falling edge of dcl_2000 at any chip connected to the iom-2000 interface. the first dcl-2000 cycle in which fsc is sampled as logic-1 after a sampling of logic-0, is considered as the first cycle of the new iom-2000 frame. when a long-pulse fsc cycle is issued, fsc always rises and falls with a rising edge of dcl_2000, and it is generated with a 50% duty cycle. t fre -10 10 ns cfsc:efscd = ? 0 ? 2) 2) fsc control register : efscd (bit 2) = ? 0 ? , i.e. no delay between dcl_2000 rising edge and fsc rising edge. ? fsc control register ? on page 239 6 26 ns cfsc:efscd = ? 1 ? 3) fsc falling edge delay after dcl_2000 rising edge t ffe -10 26 ns long-pulse fsc cycle fsc falling edge delay after dcl_2000 falling edge 4) t fff 70 ns short-pulse fsc cycle dcl_2000 = 3072 khz dcl = 4096 khz fsc clock period t fcd 125 s
peb 20570 peb 20571 electrical characteristics and timing diagrams data sheet 271 2001-03-19 preliminary figure 81 iom-2000 interface timing 3) fsc control register : efscd (bit 2) = ? 1 ? , i.e. fsc rising edge is delayed in one cycle of 61.44 mhz (16 ns) after dcl_2000 rising edge. special mode designed for working with the vip. ? fsc control register ? on page 239 4) when a short-pulse fsc cycle is issued, fsc high period is one dcl (of iom-2) cycle long. in the worst case, when dcl_2000 = 3072 khz and dcl = 4096 khz, fsc high pulse is shorter than one cycle of dcl_2000, but yet it is stable from the rising edge and until at least 70 ns after the falling edge of dcl_2000 within this single cycle. thus setup and hold times of fsc around dcl_2000 ? s falling edge are guaranteed. dcl_2000 dx dr cmd stat ch0 ch1 ch2 ch3 ch2 ch3 ch4 ch5 fsc t dsf t dhf t xdr t xdr t ssf t shf t cdr
peb 20570 peb 20571 electrical characteristics and timing diagrams data sheet 272 2001-03-19 preliminary figure 82 fsc timing iom-2000 note: usually dsp-clock is generated internally by the internal pll, in a frequency of 61.44 mhz. if on the other hand a lower frequency clcok is provided via clk_dsp input pin, the selected frequency of dcl_2000 should not exceed the frequency of dsp-clock-frequency / 4 (dsp clcok frequency devided by 4), in order to guarantee a proper operation of the delic. table 81 dcl_2000 (iom-2000 data clock) timing parameter symbo l limit values unit notes min. typ. max. dcl_2000 clock period t dcp 325 ns dcl_2000 = 3072 khz 162 ns dcl_2000 = 6144 khz 81 ns dcl_2000 = 12288 khz dcl_2000 duty cycle t ddc 48 52 % dcl_2000 fsc fsc-short t fre t fre t ffe t fff t fcd t fcd
peb 20570 peb 20571 electrical characteristics and timing diagrams data sheet 273 2001-03-19 preliminary 8.6.7 lnc0..3 (local network controller) interface timing table 82 lnc0..3 interface timing parameter symb ol limit values unit notes min. typ. max. lrxd0..3 setup time before lclk0..3 falling/rising edge t lsl 10 ns lrxd0..3 hold time after lclk0..3 falling/rising edge t lhl 14 ns lcxd0..3 setup time before lclk0..3 falling/rising edge t csl 10 ns lcxd0..3 hold time after lclk0..3 falling/rising edge t chl 10 ns ltxd0..3 delay after lclk0..3 rising edge t tdr 24 ns ltxd0..3 ltxd0..3 float after lclk0..3 rising edge t tfr 20 ns ltsc0..3 delay after lclk0..3 rising edge t scr 23 ns
peb 20570 peb 20571 electrical characteristics and timing diagrams data sheet 274 2001-03-19 preliminary figure 83 lnc0..3 (local network controller) interface timing lclk0..3 ltsc0..3 ltxd0..3 lrxd0..3 lcxd0..3 lrxd0..3 lcxd0..3 sampling with falling edge sampling with rising edge t tdr t scr t lsl t lh l t ch l t cs l t tfr t ls l t lh l t cs l t chl
peb 20570 peb 20571 electrical characteristics and timing diagrams data sheet 275 2001-03-19 preliminary note: lclk0..3 are generated with a 50% duty cycle. even though all lclks (0, 1, 2, 3) might be operated in all possible frequencies, the frequency of each one of these clocks should be configured in accordance with the ghdlcu operating mode. for more detailes see section 6.2.6.2 ? ghdlc channel mode register ? . usually dsp- clock is generated internally by the internal pll, in a frequency of 61.44 mhz. if on the other hand a lower frequency clcok is provided via clk_dsp input pin, the frequency of lclk0..3 (input or output) should not exceed the frequency of dsp- clock-frequency / 4 (dsp clcok frequency devided by 4), in order to guarantee a proper operation of the delic. figure 84 lclk0..3 timing in output mode table 83 lclk0..3 timing in output mode parameter symb ol limit values unit notes min. typ. max. lclk0..3 clock period t lcp 488 ns lclk0..3 = 2048 khz 244 ns lclk0..3 = 4096 khz 122 ns lclk0..3 = 8192 khz 61 ns lclk0..3 = 16384 kh z lclk0..3 duty cycle in output mode 48 52 % table 84 lclk0..3 timing in input mode parameter symbo l limit values unit notes min. typ. max. lclk0..3 minimum high pulse t lmh 22 ns in input mode lclk0..3 minimum low pulse t lml 22 ns in input mode lclk0..3 t lcp
peb 20570 peb 20571 electrical characteristics and timing diagrams data sheet 276 2001-03-19 preliminary note: the frequency of each lclkn pin (n = 0,1,2,3) should not exceed the maximum frequency, defined according to the ghdlcu operating mode. for more detailes see section 6.2.6.2 ? ghdlc channel mode register ? . the minimum pulse width (high or low) of lclk0..3 depends on the dsp clock frequency. usually this clock is generated internally by the internal pll, in a frequency of 61.44 mhz. in this case the values in the table above are valid. if a lower frequency for dsp-clock is provided via clk_dsp input pin, and pdc is used as input, the low/high pulse width of pdc should not be smaller then 1.5 x dsp-clock-cycle (dsp-clock-cycle is the cycle time of the provided dsp clock). usually dsp-clock is generated internally by the internal pll, in a frequency of 61.44 mhz. if on the other hand a lower frequency clcok is provided via clk_dsp input pin, the frequency of lclk0..3 (input or output) should not exceed the frequency of dsp-clock- frequency / 4 (dsp clcok frequency devided by 4), in order to guarantee a proper operation of the delic. figure 85 lclk0..3 timing in input mode note: usually clk_dsp is not used. if it is, special care should be taken regarding it ? s duty-cycle. the duty-cycle of clk_dsp should be very close to 50%, since this clock is also used for the clock-generation for the oak (phi1, phi2). table 85 clk_dsp input clock timing parameter symbol limit values unit notes min. typ. max. clk_dsp maximum frequency t cmf 61.44 mhz clk_dsp duty-cycle t cdd 48 52 % lclk 0..3 t lmh t lml
peb 20570 peb 20571 electrical characteristics and timing diagrams data sheet 277 2001-03-19 preliminary 8.6.8 jtag and emulation interface timing table 86 test interface timing parameter symbol limit values unit notes min. typ. max. test clock (jtck) period t tcj 160 ns test clock (jtck) period low t cjl 80 ns test clock (jtck) period high t cjh 80 ns tms set-up time before jtck rising edge t suj 30 ns tms hold time after jtck rising edge t hjr 30 ns tdi set-up time before jtck rising edge t dse 30 ns tdi hold time after jtck rising edge t dhe 30 ns tdo delay after jtck falling edge t odf 60 ns any output pin delay after jtck falling edge t opd 60 ns in update-dr tap controller state any input pin setup time before jtck rising edge t ipj 30 ns in capture-dr tap controller state any input pin hold time before jtck rising edge t iaj 30 ns
peb 20570 peb 20571 electrical characteristics and timing diagrams data sheet 278 2001-03-19 preliminary figure 86 test-interface (boundary scan) timing table 87 reset and resind (reset indication) timing parameter symbo l limit values unit notes min. typ. max. reset pulse width t rpw 430 ns resind pulse width t riw 500 800 s resind deactivation after reset deactivation t rdr 800 s tck tms tdi td0 any_input any_output t tcj t cjl t cjh t suj t hjr t dse t dhe t odf t opd t ipj t iaj
peb 20570 peb 20571 electrical characteristics and timing diagrams data sheet 279 2001-03-19 preliminary figure 87 reset indication timing figure 88 clockout timing table 88 clockout timing parameter symbol limit values unit notes min. typ. max. clkout period t ckp 488 ns clkout = 2048 khz 244 ns clkout = 4096 khz 122 ns clkout = 8192 khz 65 ns clkout = 15360 khz 61 ns clkout = 16384 khz clkout duty-cycle 48 50 52 table 89 l1_clk timing parameter symbol limit values unit notes min. typ. max. l1_clk period t lcp 65 ns l1_clk = 15.36 mhz 130 ns l1_clk = 7.68 mhz l1_clk duty-cycle 48 50 52 % reset resind t rpw t riw t rdr clkout t ckp
peb 20570 peb 20571 electrical characteristics and timing diagrams data sheet 280 2001-03-19 preliminary figure 89 l1_clk timing figure 90 xclk timing table 90 xclk timing parameter symbol limit values unit notes min. typ. max. xclk period 1) 1) xclk is always an input. the frequencies, which are specified in the table above, should be provided by the user. when xclk is used as a reference clock for the internal dcxo-pll, one of these specified frequencies must be used, to guarantee proper work of the delic. t xlp 488 ns xclk = 2.048 mhz 651 ns xclk = 1.536 mhz 125 sxclk=8khz xclk minimum high period t xlh 50 ns xclk minimum low period t xll 50 ns l1_clk t lcp xclk t xlp t xll t xlh
peb 20570 peb 20571 electrical characteristics and timing diagrams data sheet 281 2001-03-19 preliminary figure 91 refclk timing table 91 refclk timing parameter symbol limit values unit notes min. typ. max. refclk period 1) t rfp 1.953 s refclk = 512 khz 125 srefclk=8khz refclk minimum high period t rfh 50 ns refclk minimum low period t rfl 50 ns 1) refclk may be used either as an input or as an output. when used as an input, the frequencies, which are specified in the table above, should be provided by the user. when refclk is used as a reference clock for the internal dcxo-pll, one of these specified frequencies must be used, to guarantee proper work of the delic. refclk t rfp t rfh t rfl
peb 20570 peb 20571 application hints data sheet 282 2001-03-19 preliminary 9 application hints 9.1 delic connection to external microprocessors figure 92 delic connection to intel 80386ex (demuxed configuration) a0 a(5..1) ad(7..0) dreqr dreqt dack d(7..0) csn wr rd intr drq0 drq1 ble a(5..1) 80386ex vcc 2.7v-3.6v,25mhz delic ale cs wr rd ireq 80386ex.vsd dack0 dack1
peb 20570 peb 20571 application hints data sheet 283 2001-03-19 preliminary figure 93 delic connection to infineon c165 (demuxed configuration) hold delic 20mhz hlda a(5..0) ad(7..0) csn wr rd intn hold hlda 8237 drq0 drq1 dack0 dack1 hold hlda 8237 dreqr dack wr ireq rd ale cs d(7..0) a(5..0) dma controller c165.vsd infineon c16x dreqt
peb 20570 peb 20571 application hints data sheet 284 2001-03-19 preliminary 9.2 delic worksheets figure 94 delic-lc pcm unit mode 0 (4 ports with 2 mbit/s) dsp pcmu data buffer 0xa000 0xa01f 0xa020 0xa03f 0xa040 0xa060 0xa05f 0xa07f 0xa080 0xa09f 0xa0a0 0xa0bf 0xa0c0 0xa0df 0xa0e0 0xa0ff in 0 in 1 in 2 in 3 out 0 out 1 out 2 out 3 txd0 txd1 txd2 txd3 rxd0 rxd1 rxd2 rxd3 tsc0 tsc1 tsc2 tsc3 0 15 pcr address: 0xd060 dr 00: 4 x 2.048 mbit/s 01: 2 x 4.096 mbit/s 10: 1 x 8.192 mbit/s 11: 1 x 16.384 mbit/s dc 0: single clock 1: double clock od 0: push pull mode 1: open drain mode a 0: pcmu is idle 1: pcmu is active icdb 0: frame buffer 0 accessed by the dsp 1: frame buffer 1 accessed by the dsp sfh 0: the first 128 time-slots are used 1: the second 128 time-slots are used 0 15 ptscr0 address: 0xd062 set and read 0xd063 reset and read 0 15 ptscr1 address: 0xd064 set and read 0xd065 reset and read 0 15 ptscr2 address: 0xd066 set and read 0xd067 reset and read 0 15 ptscr3 address: 0xd068 set and read 0xd069 reset and read 0 15 ptscr4 address: 0xd06a set and read 0xd06b reset and read 0 15 ptscr5 address: 0xd06c set and read 0xd06d reset and read 0 15 ptscr6 address: 0xd06e set and read 0xd06f reset and read 0 15 ptscr7 address: 0xd070 set and read 0xd071 reset and read 0 15 pdpr address: 0xd072 00000000
peb 20570 peb 20571 application hints data sheet 285 2001-03-19 preliminary figure 95 command/ indication handshake of general mailbox mgen 0xd143 (msb) 0xd142 (lsb) 0xd144 (all) 0x43 0x42 mdt0 mdt1 mdt2 mdt3 mdt4 mdt5 mdt6 mdt7 0xd100 0xd102 0xd104 0xd106 0xd108 0xd10a 0xd10c 0xd10e 0x07 0x06 0x09 0x08 0x0b 0x0a 0x01 0x00 0x03 0x02 0x0d 0x0c 0x0f 0x0e 0x05 0x04 mcmd ( p -> dsp) mbusy ( p <- dsp) 0xd141 (inh. bel.) bit 7 0xd140 (8 bit) 0x41 0x40 mdt8 mdt9 mdt10 mdt11 mdt12 mdt13 mdt14 mdt15 0xd110 0xd112 0xd114 0xd116 0xd118 0xd11a 0xd11c 0xd11e 0x17 0x16 0x19 0x18 0x1b 0x1a 0x11 0x10 0x13 0x12 0x1d 0x1c 0x1f 0x1e 0x15 0x14 p expanded mailbox p mailbox mailbox-synchr. p dsp ogen 0xd163 (msb) 0xd162 (lsb) 0xd164 (all) 0x63 0x62 odt0 odt1 odt2 odt3 odt4 odt5 odt6 odt7 0xd120 0xd122 0xd124 0xd126 0xd128 0xd12a 0xd12c 0xd12e 0x27 0x26 0x29 0x28 0x2b 0x2a 0x21 0x20 0x23 0x22 0x2d 0x2c 0x2f 0x2e 0x25 0x24 ocmd ( p <- dsp) obusy ( p -> dsp) 0xd161 (16 bit) bit 15 0x61 (8 bit) odt8 odt9 odt10 odt11 odt12 odt13 odt14 odt15 0xd130 0xd132 0xd134 0xd136 0xd138 0xd13a 0xd13c 0xd13e 0x37 0x36 0x39 0x38 0x3b 0x3a 0x31 0x30 0x33 0x32 0x3d 0x3c 0x3f 0x3e 0x35 0x34 dsp expanded mailbox dsp mailbox mailbox-synchr. p dsp 0xd160 (8 bit) (inh. bel.) 0x60
peb 20570 peb 20571 application hints data sheet 286 2001-03-19 preliminary 9.3 pcm output driver anomaly when applying the pcm outputs in a bus configuration with pull-ups to 5 v the output drivers of the delic have an irregular behavior. as can be seen from the illustration below, the pcm output drivers txdn (n=0..3) continue to drive ? high ? level even outside the time slot enabled by tsc. this error occurs only if the last bit in the time slot is a ? 1 ? . in this case no problem occurs if another pcm port drives a ? 0 ? in the neighbor time slot. in other words this means that the output driver drives 3.3 v for a certain time against the 5 v pull-up. as soon as a neighbor time slot is driven to ? 0 ? by another port the delic stops driving immediately. as the occurring current is no problem for the delic, this behavior is uncritical. figure 96 behavior of output driver if last bit is ? 1 ? figure 97 behavior of output driver if last bit is ? 0 ? tsc txd 3.3 v 5 v 3.3 v 0 v 0 v tsc txd 3.3 v 5 v 3.3 v 0 v 0 v
peb 20570 peb 20571 application hints data sheet 287 2001-03-19 preliminary 9.4 reset behaviour figure 98 guaranteed reset behaviour if the delic dsp uses the internal 61.44 mhz clock, the reset value of the delic registers can only be guarantied 200 ns after the rising edge of the reset signal. if an external dsp clock is used, the reset behaviour is normal, e.g. the reset values are valid after the falling edge of the reset signal. in order to guaranty the reset behaviour of the delic in any case, the external circuity as shown in figure 98 is recommended. during reset, the dsp is clocked externally. when reset is deactivated the internal dsp clock is used. note: the frequency of the external clock is not important. the higher the frequency the faster the reset values are valid. a clock frequency in the range of several mhz (e.g. 4 mhz) is recommended. delic-lc/-pb reset dsp_frq clk_dsp external clock
peb 20570 peb 20571 glossary data sheet 288 2001-03-19 preliminary 10 glossary ahv-slic peb 4165 high voltage part of slic cmos complementary metal oxide semiconductor co central office codec coder decoder dc direct current dect digital european cordless telecommunication delic dsp embedded line and port interface controller (peb 20570, peb 20571) dsl digital subscriber line dsp digital signal processor hdlc high-level data link control ieee institute of electrical and electronic engineers info u- and s-interface signal as specified by ansi/etsi i/o input/output iom-2 isdn-oriented modular 2nd generation iom-2000 proprietary isdn interface for s/t and u pn isdn integrated services digital network itu international telecommunications union p micro processor octat-p octal transceiver for u pn -interfaces (peb 2096) lt-s line termination-subscriber lt-t line termination-trunk pll phase-locked loop pbx private branch exchange afe 4-channel analog front end of u-transceiver (peb24902) dfe 4-channel digital front end of u-transceiver (peb24911) quat-s quadrupletransceiver for s/t-interface (peb 2084) slicofi-2 peb 3265 dual channel codec + low voltage part of slic
peb 20570 peb 20571 glossary data sheet 289 2001-03-19 preliminary socrates shdsl one chip rate adaptive transceiver with embedded start up s/t two-wire pair isdn interface tap test access port
peb 20570 peb 20571 index preliminary data sheet 290 2001-03-19 11 index a applications 7 b block diagram 70 block diagram of the delic-lc 3, 125 boot strap pin setting 130 d differences delic-lc - delic-pb 69 f features delic-lc 4 delic-pb 4 i interfaces iom-2000 41 overview 40 interrupts 66 iom-2000 command and status interface 72 iom-2000 frame structure 42 j jtag test interface 67 l logic symbol 6 p pin definitions 12, 24 pin diagram 10 principle block diagram of the delic-pb 3 s s/t state machine 54 strap pin definitions 38 t transiu initialization 71 overview of features 71 u u pn line interface frame structure 76 v vip initialization 72
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